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Cadence, Mentor spar in high-speed realm

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design? Mentor Graphics? interconnects? Ibis Macromodeling Library Task Group? standard?

An ad hoc group is trying to come to grips with escalating problems arising from a lack of standards for simulating chip interconnects as they scale up to 5Gbps and beyond. The issue has pitted Cadence Design Systems Inc. and Mentor Graphics Corp. in a battle to gain support for competing solutions.

Two proposals are on the table at the Ibis Macromodeling Library Task Group. But, so far, neither has been demonstrated to be a clear winner.

"We need a new generation of EDA tools for serial links. Modeling is a particularly vexing problem that is a long way from being sorted out," said Todd Westerhoff, who leads a high-speed signal integrity group in the router division at Cisco Systems Inc.

The industry is rapidly moving to a host of fast serial interfaces to link chips, boards and systems. But somewhere between 3.125Gbps and 6Gbps, high-speed signals take a troubling turn. Chipmakers must resort to increasingly complex techniques such as transmit pre-emphasis and receiver equalization to send and recover a clock and a signal.

Conventional testing methods using eye models on an oscilloscope are no longer useful when such techniques are used. In addition, traditional transistor-level Spice models are not effective when traffic of as much as a million bits must be simulated to test chip-to-chip links. Thus, chipmakers are starting to develop their own homegrown environments in C or Matlab to create chip models that OEM customers can drop into their system simulations.

"This works well as long as you are only using one vendor's parts, but all the silicon vendors have their own tools and environments with chip models tied to them," Westerhoff said. "They don't work together, and they have no interoperability with traditional Spice or Ibis modeling tools."

The situation will only get worse as speeds increase. Chipmakers expect to use an ever-more-complex array of standard and proprietary signal-conditioning and filtering techniques that exhibit different effects on different PCBs and cables. As they do, signals are already appearing on an oscilloscope as a closed eye.

"There is nothing you can measure. This is what we are headed into," Westerhoff said. "This is well beyond what anyone has done in signal integrity before."

So far, designers must simply tolerate more uncertainty than they would like in their models. But as speeds increase, they could be forced into building board-level prototypes to test interconnectsa move that would take a toll on both costs and time-to-market.

Cadence vs. Mentor
The holy grail is a single simulation approach suitable for high-speed designs that will adequately model the chip signals and the effects caused by the nuances of the board trace or cable between them. The approach should be one that any chip or EDA vendor can readily support while protecting proprietary silicon intellectual property (IP).

In June, Cadence and IBM teamed up to present to the Ibis Macromodeling group the idea of creating an open application programming interface for modeling high-speed signals. Texas Instruments has expressed some support for the concept.

Cadence has already produced an updated version of its PCD SI GXL tool with new algorithmic modeling capabilities. The tool uses the new API and can simulate traffic of 10 million bits within an hour. Cadence is testing the approach with two chipmakers and three design groups inside a systems company.

"We are trying real models to find any issues we have with the API, and extend it according to the needs of the chip and system companies," said Hemant Shah, a product-marketing director in Cadence's PCB group.

How it's done
Cadence is attempting a top-down approach to complex modeling that lets chipmakers create algorithms in the form of dynamic link libraries (DLLs) that can plug into any compliant simulator. Users can add various jitter characteristics and clock-recovery mechanisms and protect IP via any encryption standard.

According to a Cadence presentation, the approach uses several steps. The simulator tries to characterize the trace or cable that defines the channel. It sends an impulse response to the transmitter and measures its reaction. The modified impulse response is then sent to the receiver and changes are measured again. The program then does a bit-by-bit simulation and sends a final waveform to a receiver DLL.

But Cadence's top competitor in PCB design tools, Mentor Graphics, vetoes the idea of a new API. Instead, it wants to stick with the VHDL-Analog Mixed-Signal (AMS) tools supported in its existing PCB-design products. Mentor first rolled out VHDL-AMS support in its ICX Version 3.0 tool in 2004.

"If we are going to support C modeling, we would like to see a standard such as the IEEE 1666 for SystemCnot a new, proprietary alternative," said Ian Dodd, a high-speed design architect with Mentor who has been active in the Ibis Macro group.

"I'm not so sure we necessarily need new EDA tools," said Dodd. "It's hard enough just to get Ibis models from chip vendors. It's not realistic to expect them to compile chip models for every design environment," as required in the Cadence proposal.

A drawback of the Mentor approach is that there are no major companies, beyond Mentor and Agilent Technologies, that support the VHDL-AMS language in their high-speed design tools. Cadence claims VHDL-AMS is simply not up to the job of modeling complex functions such as decision-feedback equalization.

"AMS has its place, but working with IBM and TI, we have found that at 6Gbits and beyond, it is not natural. Our idea is to use AMS up to a certain point, and beyond that, we need an algorithmic simulator," said Shah of Cadence. "AMS is not designed for algorithmic modeling and does not lend itself to it."

Not so, said Dodd. "AMS as it is presently defined is capable of doing just about anything, including mechanical and plumbing design. It's extremely flexible," he said.

Dodd pointed out that some Ibis Macro members use Verilog digital tools to create their 5Gbit-plus Serdes. Mentor will support Verilog-AMS if users demand it, he added.

Arpad Muranyi, a signal-integrity engineer at Intel Corp. and a co-founder of the original Ibis effort, chairs the Ibis Macro group. He takes a balanced view of the continuing debate.

Initially, the group developed AMS libraries now posted on its Website as an aid for signal-integrity engineers, many of whom are not familiar with the language. The group has developed many basic AMS libraries for elements such as resistors, capacitors, inductors and buffer algorithms.

However, the libraries will have to be extended to handle rising issues concerning IP encryption and more complex functions, such as FIR filters. On the other hand, "the advantage of the API is you are not restricted to the AMS language," Muranyi said. However, the goal of the Ibis group is to avoid any technology closely tied to any one vendor's product, he added.

Unclear outlook
While the problem is clear, the time frame for a solution is not. The group is still weighing the pros and cons of the two proposals.

"The sooner we get a solution, the better, but we have no set date," Muranyi said. "Ibis is based on all volunteer work, so we move forward as fast as we can, but we can only move so fast." What the Ibis Macro group needs most is "more involvement from the EDA industry," he said.

Westerhoff of Cisco agreed. "A lot of EDA vendors have brought out tools for high-speed serial-link design that are in various stages of maturity, but we are a long way from stability in these tools," he said.

"The Ibis committee is the right forum to get everyone together," added Shah.

The overarching Ibis group is known for its behavioral-simulation technique, which uses data about the I/O of chips so as not to reveal proprietary design information about the silicon itself. Ibis stands for Input Output Buffer Information Specification.

- Rick Merritt
EE Times




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