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Tool compiles C source code to RTL

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:high-level compilation technology? TCP/IP intellectual property? C-language compiler? Verilog-to-RTL compiler? transport offload engine?

CebaTech Inc., launched in 2004 by a group of chip designers who had developed high-level compilation technology for their own needs, recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.

CebaTech was started by designers who had developed a behavioral Verilog-to-RTL compiler at Sandgate Technologies in 2000. At that time, Tim Sullivan, former general manager of Lucent's optical area networking division, contracted with Sandgate engineers to build a 1Gbyte transport offload engine. Sullivan later joined up with three former Sandgate engineers to launch CebaTech, which he heads as president and CEO.

CebaTech was expected to divulge plans to offer a tool that can compile C-language descriptions into synthesizable RTL code, as well as compile untimed C into cycle-accurate C models. The company claims to support an ESL design methodology that allows an entire SoC to be coded in C and to run in a native C software environment where the cycle-accurate model precisely represents the behavior of the generated RTL.

Chad Spackman, CTO of CebaTech and former president of Sandgate, said that Sandgate's experience with behavioral Verilog compilation had shown "that behavioral flows are just king in terms of reducing the manpower required to do a chip." While most ASICs require large development teams, Spackman said, two people had designed a full TCP/IP offload chip in a standard 12-month ASIC turnaround time.

But there was a problem: The chip was difficult to verify, and there were four respins.

With the launch of CebaTech, the team took a different approach, compiling RTL code directly from C. Verification can be completely handled in the C-language environment using the cycle-accurate models, according to the company.

"I think the manpower savings are going to be about 10 to 1," Spackman said. "Once we produce RTL, it's deemed to be correct. We have methods to prove that in a live environment, C code can communicate over live networks. The goal is large designs without any respins."

Unlike most EDA providers, the 25-person CebaTech is using its own tools to design products. Its initial IP offerings are based on the OpenBDS TCP/IP stack. They will include an Internet Protocol version 4 (IPv4) module, packet filter module, UDP protocol module, TCP protocol module, iSCSI initiator and target protocols, IPsec module and IPv6 module. CebaTech will also provide complete ICs for specific requests in those areas.

IP or EDA
So is CebaTech an IP provider or an EDA company? "It's a question that's asked a lot of times, and the answer is that it has to be both," Spackman said. "But a compiler requires a tremendous amount of development effort and support, so it will be a substantial investment."

CebaTech is entering a crowded ESL landscape, with many providers of C-language tools. But the startup has some different ideas.

For one, said Spackman, CebaTech believes architecture should be coded into the C-language source, not added in by a behavioral synthesis tool. Otherwise, he said, the tool will add parallelismand as soon as it does, the source code no longer represents the functionality of the device.

C source code, therefore, must be "structured by an architect to represent good hardware," Spackman said. It's up to the designer to decide what needs to be represented by parallelism, and to code the C source that way, using what CebaTech calls attributes. Typically, only about 2 percent of the original code stack needs to change, Spackman said.

The restructuring takes some time: A CebaTech design team worked on a TCP/IP stack with about 50,000 lines of code, Spackman said, and it took four people six months to restructure the code. But all of the code restructuring, he noted, can be done by software people, with some guidance from a hardware architect. No additions to the C language are required.

In other examples, he said, it took about three days of restructuring to achieve a fourfold clocking improvement in RTL for a Viterbi decoder, and minutes to generate RTL with increased bit precision.

Behavioral synthesis
Whether CebaTech is offering behavioral synthesis is a matter of debate. A traditional definition of behavioral synthesis would include resource allocation and scheduling. CebaTech's compiler handles the scheduling with "clock insertion," Spackman said, but does not do resource allocation. The designer handles that task in the C source code.

The cycle-accurate C produced by the compiler can be recompiled with a "plain old C compiler" and run back in place of the original C code, Spackman said. That reportedly enables functional testing in native C software environments using live networks, executing hundreds of millions of instructions per second.

"Every module in that C code is strictly accurate in terms of the time it takes to do something per clock cycle," Spackman said. "It behaves just as RTL would in a simulator. It so precisely represents the RTL that we don't need to simulate the RTL."

But he is also realistic. "We're very aware of what RTL groups are used to, and we do not expect them to simply trust us and say that simulation can go now," he said.

More likely, he said, designers will mix RTL blocks with cycle-accurate C blocks in their simulations. Another possibility would be formal verification between the cycle-accurate C models and their RTL counterparts.

The CebaTech compiler is slated to be in beta testing this month and to be available at the end of the year, with pricing to be determined. Meanwhile, the company promises that its IP will offer an order-of-magnitude difference in pricing over competitive offerings, simply because the development costs are so much lower using CebaTech's ESL flow.

- Richard Goering
EE Times




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