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Solving the MCP memory test challenge

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Kurt Gusinow? Verigy? storage? spotlight? handset memory?

The convergence of phone, multimedia and PDA functionalities in today's mobile devices combined with ever-shrinking form factors is driving manufacturers to use different memory packaging solutions. Application processors of modern phones allow the devices to act as PDAs, portable game players and TVs. These require NAND flash to store the complex programs and mobile SDRAM performance to provide the best possible user experience.

Multichip packages (MCPs) are the standard for cellphones, with nearly all modern cellphones having at least one MCP. Using MCPs allows manufacturers to offer new multifunction devices while maintaining small form factors. MCPs offer a small footprint at low cost with reasonable flexibility. Because the MCP only includes memories, the design of the processor is independent of the memory specifics, which is important with DRAM's and NAND's fast turns and short life cycles. While system-in-package and PoP, and other technologies such as package-in-package are being adopted for the 3D packaging market, MCPs are expected to continue to dominate for the next five years.

Testing MCPs
The current standard method for testing complex MCPs is to test them on multiple testers. First, the SDRAM is tested on a DRAM tester. The MCP is then transferred to another tester with another loadboard that connects the NOR/SRAM to be tested. Finally, the MCP is moved to a third tester, where a third loadboard connects the NAND to be tested. The three insertions increase the total test time of the MCP, the number of loadboards needed for each device and overall test-floor complexity. This increases the overall cost of test and triples the yield-loss due to parts damaged through handling.

While a standard memory tester reduces the cost of test by testing as many devices in parallel as possible, they are limited to testing devices with less than 64 pins, which is not sufficient for the complex MCP. This problem is further aggravated with DRAM testers, which have a limited number of bidirectional pins, often as few as nine per site.

Using a tester that supports testing of devices with more than 64 pins would solve the multiple insertion problem, but because the SRAM and DRAM finish testing much more quickly than the NOR and NAND, it would result in a low utilization of test resources. If the memories must be tested sequentially, the test resources connected to the memories not currently under test sit idle. On average, as much as two-thirds of the tester could sit idle. In both scenarios, one is paying for resources which may sit idle most of the time.

Software re-route
The solution to this MCP testing challenge is to develop a software re-routable interface technique for connecting tester resources to the specific pins being tested. This allows for testing the MCP in a single insertion and at a high parallelism while ensuring highest tester utilization.

The first obstacle lies in the sheer number of signals to be re-routed. If 40 signals per device must be re-routable to one of four device pins, a minimum of 120 relays per site are required. If 64 devices are tested in parallel, 7,680 relays are required. This takes up a great amount of space and burns a lot of power. It also creates a significant reliability risk.

While discrete FET switches help with the board space, their capacitance and trace-length stubs can affect the frequency performance of the device under test. If MCPs only had flash, the performance degradation might be acceptable, but mobile SDRAMs are already running at 133MHz, and mobile games will surely drive even higher performance. High-performance FETs are available, but they are quite sensitive to ESD, which is a liability from the reliability perspective.

Using a high-performance ASIC would resolve many of these issues. Trace-length stubs are minimized and tremendous switching densities can be achieved. However, the long lead times and high development cost for such an ASIC require that this switching matrix be device-independent. It would be cost-prohibitive to redesign this matrix for every device to be tested. An additional interface layer is needed. This creates additional challenges because it requires the use of a high-density, highly reliable and high-performing interconnect. Additionally, every tester channel must have the same functionality. Otherwise, the routing from the switching matrix to the device pin will be extended, degrading performance and adding channel capacitance.

The flexibility of having identical channels also offers the benefit of reusing the device-specific interface or socket board. Because MCPs are designed for a specific mobile appliance, there is no consistency in pinouts for a given package.

Small package
The central component of Agilent's Programmable Interface Matrix is the Kiowa high-performance ASIC. Each of these ASICs can switch eight tester channels between 64 device pins. To accommodate 1,024 of these per test head, a 100-pin chip-scale package was chosen. The high-speed serial bus minimizes the number of traces that must be run to each ASIC, resulting in a less complex, smaller board.

To achieve the required performance, the switching matrix cannot increase the signal path capacitance substantially. Increased capacitance will slow down the rise times of high-performance memories, and many lower-performance mobile memories cannot drive a highly capacitive line. To this end, line capacitance was minimized by simplifying the signal path as much as possible and using low-capacitive gates. The routing was implemented to minimize the stub length for each switch path, as each stub increases the capacitance for the line. Finally, each channel is isolated from the other three channels to minimize any crosstalk between channels.

Reducing test costs
Using a switching network with an all I/O tester increases tester resource utilization when testing MCPs. This allows for higher parallelism and shorter test times. The switching network also allows complex MCPs to be tested in one insertion, eliminating the need for multiple loadboard designs for each new MCP.

These increasing densities will continue to drive the higher level of integration that MCPs provide. As the stacks grow higher, providing economic testing becomes increasingly difficult. A switching matrix can reduce the cost of test of these devices by up to 75 percent.

- Kurt Gusinow
Test Market Development Manager
Semiconductor Test Systems
Verigy Ltd

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