Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Interface
?
?
Interface??

New cPCIBPMC versions feature extended temperature

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dynamic Engineering? cPCIBPMC? cPCIBPMC6UET? cPCIBPMC3U64ET?

Dynamic Engineering's cPCIBPMC3U64ET

Responding to customer request, Dynamic Engineering said it has developed two extended temperature versions of its cPCIBPMC design. The new versions involved switching to a new bridge to meet the extended temperature and timing requirements. The new bridge promises new features including the ability to operate the PMC side at a higher clock rate than the cPCI side. It also has built-in features for local address spaces, using the PMC clock in monarch mode for the secondary side, and operating in transparent or non-transparent modes.

The second design "cPCIBPMC6UET" is a 6U 4HP version with two PMC slots. The 6U version has both PMC I/O connectors routed with equal length traces to J3 and J5. A PIM Carrier is available for the 6U model to support rear panel I/O.

The cPCIBPMC3U64ET (cPCI to PMC) adapter/carrier converter card enables the installation of a PMC card into a standard cPCI slot. The cPCIBPMC3U64ET has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/64 with 33/66MHz bus operation, the 3U card is wired for 64bit PCI operation with pull-ups on the control lines to allow use in a 32bit system. The PMC bezel connector is mounted though the cPCI mounting bracket. The cPCIBPMC3U64ET is an extended temperature design. Conformal Coating is an option.

The PCI bus is interconnected to the PMC via 64bit 66MHz capable layout. The slower and more narrow device will determine the interface characteristics. The supplied dip-switch is used to control the bridge configuration. The user can select the clock rate on both buses and has access to the GPIO bits. PME and the Interrupt request lines are routed from the PMC to the cPCI connector.

The PCI VIO is interconnected to the primary side of the bridge. The secondary side of the bridge has programmable VIO allowing 5V PMCs to be used in 3V systems and vice-versa. The voltage select pins are not installed on the cPCIBPMC3U64ET. The bridge will automatically adapt to the PCI bus reference voltage. Many PMCs are universal and can work with 3.3V or 5V cPCI backplanes. The secondary side has a shunt for the user to select 5V or 3V operation.

The cPCIBPMC3U64ET follows the PMC specs for maximum power consumption and heat dissipation. The power is routed from the cPCI to PMC connectors with mini-planes each of which is rated for more than the maximum PMC draw.

With 3U cPCI, J2 has two definitionsin a 64bit PCI implementation J2 has the upper A/D and control signals; and in a 32bit PCI implementation, it has the rear panel IO. The cPCIBPMC3U64ET has the upper part of the PCI bus connected to J2. In addition the commonly used Ethernet and I?C, pins from the Jn4 and Jn1 are optionally connected to reserved pins on J2 to allow rear panel I/O for those signals.




Article Comments - New cPCIBPMC versions feature extend...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top