Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Xilinx upgrades analysis software to support 65nm FPGAs

Posted: 06 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? PlanAhead? Virtex-5? FPGA? analysis software?

Xilinx Inc. has announced the immediate availability of the 8.2 version of its PlanAhead hierarchical design and analysis software with support for the company's newest Virtex-5 LX family of 65nm FPGAs. Used in conjunction with the Xilinx Integrated Software Environment (ISE) design tools, PlanAhead 8.2 software promises a two-speed grade performance and cost advantage over competing offerings.

Leveraging the unique advantages of the Virtex-5 LX ExpressFabric technology, 550MHz DSP48E slices and flexible clock management tiles, Xilix said the upgraded software features a robust, accurate signal integrity analysis capability and improved graphical interface that allows designers to rapidly evaluate multiple design implementation strategies to accelerate timing closure.

PlanAhead 8.2 provides functionality to check limits for weighted average simultaneous switching output (WASSO) analysis. This new functionality allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA. As a result, designers can more effectively manage ground bounce on I/O banks for better signal integrity, the company explained.

The software extends the capabilities of the ExploreAhead design exploration utility to allow users to run multiple implementations with different floorplans of their design to achieve optimal results. These can be queued or optionally run in parallel when multiple processors are available. In addition, the ExploreAhead tool offers improved directory management, process management and integration with the FPGA bitstream generation application in the ISE environment.

Other PlanAhead 8.2 enhancements include improved management of physical constraints and viewing of the I/O pin properties for a much more streamlined design exploration and floorplanning environment, the company said.

Article Comments - Xilinx upgrades analysis software to...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top