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Synopsys, SMIC team on ref design flow 3.0

Posted: 07 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? SMIC? reference design flow 3.0? RTL-to-GDSII flow? Galaxy Design?

Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) announced that the two companies have jointly developed and deployed reference design flow 3.0.

The companies' Professional Services worked together on the complete RTL-to-GDSII flow, which is based on the Synopsys Galaxy Design and Discovery Verification Platforms and SMIC's advanced 90nm process. The proven flow incorporates a broad range of automated low-power and design-for-manufacturing (DFM) capabilities to help shorten time-to-market, reduce risk and ensure predictable success for complex SoC designs.

SMIC's low-power process and the reference design flow were validated using SMIC's multiple voltage standard cell libraries, low-power design kit, memory compiler and I/O. The flow features Synopsys' Galaxy Design Platform solutions for RTL synthesis and test, physical implementation and signoff. Advanced closure features in the flow target concurrent timing, power optimization and signoff, including SI prevention, analysis and repair.

The reference design flow 3.0 is derived from the design flow in Synopsys' Pilot Design Environment and can be extended and enhanced by designers to address design-specific requirements. Advanced low-power capabilities include level shifter and isolation cell insertion, voltage area creation, multiple voltage power mesh creation, level shifter and isolation cell placement optimization, multiple voltage-aware CTS and multiple voltage-aware physical verification, which can reduce leakage power dissipation by 30 percent.

The capabilities were validated using SMIC's low-power design kit, which consists of a level shifter, isolation cell and clock gating cell. DFM features include via optimization, as well as filler cell and filler cap insertion. Test capabilities in the flow reduce test data volume and time.




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