Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Interface

Synopsys unrolls connectivity IP for SMIC 130nm tech

Posted: 07 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? SMIC? DesignWare? mixed-signal PHY-IP? MSIP?

Synopsys Inc. has announced the expansion of its DesignWare mixed-signal intellectual property (MSIP) portfolio with the release of connectivity IP for Semiconductor Manufacturing International Corporation's (SMIC's) 130nm technology. The mixed-signal PHY IP supports different protocols such as USB, PCIe, SATA and XAUI.

DesignWare mixed-signal PHY IPs consume at least 30 percent lower than competitive solutions, the company said. This makes them suitable for mobile applications and saves on packaging costs. They are also designed to have the lowest area, noise and jitter performance in the industry, Synopsys explained, and feature a robust architecture that makes them insensitive to process, voltage and temperature variations. On-board diagnostics on the PCI Express, SATA and XAUI PHYs also enable inexpensive at-speed production testing that significantly reduces test-time budgets and costs, said the company.

"We worked closely with SMIC to ensure that the low power and area of our PHYs and their high-yield characteristics are retained when manufactured in SMIC's 130nm process," said Guri Stark, marketing VP for the solutions group at Synopsys. "We will continue collaborating with SMIC and aligning our mixed-signal IP roadmap with their technology roadmap to meet the demands of our mutual customers."

DesignWare USB 2.0 nanoPHY IP, and DDR2 and mobile DDR memory interface I/Os are alrady available. PCI Express, SATA and XAUI PHYs are expected to be available in Q4 2006.

Article Comments - Synopsys unrolls connectivity IP for...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top