'Signoff quality' timing tool rolls for 65/45nm designs

Using multiple timing-analysis tools has become unmanageable at the 65nm and 45nm nodes, according to executives from Cadence Design Systems Inc., which introduced the Encounter Timing System, described as a "signoff-quality" timing product for nanometer SoC design.

The majority of today's design flows employ two timing-analysis tools—one for implementation and a second for signoff (almost always Synopsys' PrimeTime, considered as the industry's de facto standard for final static timing and signal integrity signoff). When results from the separate tools don't correlate, designers are forced to tinker with designs until they do.

This two-tool solution is inconvenient, but manageable at the 130nm node, said David Desharnais, director of product marketing for the Encounter platform. At 45nm, however, the correlation between different timing infrastructures is nearly impossible, based on the number of complex effects, Desharnais said.

"We are starting to see some cracks [in the two-tool system] at 90," Desharnais said, "but at 65 and 45nm, it becomes a must."

"At 130 and 90nm, there is not that much stuff that you need to correlate," said Eric Filseth, VP of product marketing for the Encounter platform. "As you head into 65 and 45nm, you have a lot more low-level management stuff you have to worry about, and the timers have to agree on more things."

Just as Magma Design Automation Inc. did last year with a flow of products from its Cobra initiative, Cadence says it provides users with "signoff in the loop" capability. This concept claims to eliminate the need for "throwing designs over the wall" to do PrimeTime final timing signoff, offering instead the accuracy to perform a final signoff within the design flow.

Gary Smith, chief EDA analyst at Gartner Inc., said the concept itself is nothing new. Customers would love to simplify their flows with one timing-analysis tool, he suggested, but they cannot abandon PrimeTime without comparable accuracy.

"PrimeTime has been the signoff-timing—although not necessarily SI [signal integrity]—analyzer of choice," Smith said. "Therefore, there is only one good reason to use any other timing analyzer in your flow, and that is that it's more accurate than PrimeTime. That is changing, though. As Magma, and now Cadence, start eating into Synopsys' market share, foundries are starting to accept the Magma and Cadence timing tools as signoff tools."

Cadence's Encounter Timing System is said to provide signoff-quality timing analysis for both logic design and physical design. The tool, built on the Encounter platform, provides nanometer physics modeling, including IR drop, SI delay, and glitch and constraint checking (Cadence said a statistical-timing-analysis capability is still under development).

The tool also features a capability called global timing debug, said to provide a productivity boost for identifying timing failures. According to Desharnais, global timing debug alleviates the manual step of poring over various reports to diagnosis and debug failures. A graphical interface enables designers to visualize block- and chip-level timing in the global context, he said, including providing "what if" and bottleneck analysis, along with the ability to debug multiple paths concurrently.

The Encounter Timing System is the product of many months of development, said Desharnais and Filseth, who emphasized that the tool has been silicon-validated at major foundries and ASIC suppliers. The tool offers "unmatched" SI and IR accuracy for nanometer effects, the executives said, employing Cadence's Celtic nanometer delay calculator and VoltageStorm power grid verification technology. The tool also supports Liberty libraries, as well as Cadence's Effective Current Source Model.

The product is available now. The Encounter Timing System L version is intended for mostly front-end static timing analysis for all logic and physical-design signoff at 0.15μm and above. The XL version of the product offers SI- and IR-aware timing analysis for physical-design signoff for 130 through 65nm. A high-end GXL version, focused on 45nm and 32nm node design, is planned for next year. Pricing information was not disclosed.

- Dylan McGrath
EE Times