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Cadence, SMIC co-develop digital ref flow for 90nm tech

Posted: 08 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? SMIC? Semiconductor Manufacturing International Corp.? reference flow? 90nm?

Cadence Design Systems Inc. and Semiconductor Manufacturing International Corp. (SMIC) have jointly developed a low-power digital reference flow to support SMIC's advanced 90nm process technology. The reference flow, which includes support for the Cadence Encounter Timing System, is now available to address the increasing needs of designers developing ICs for the computing, consumer, networking and wireless markets.

The reference flow incorporates the Cadence Encounter digital IC design platform and Cadence design for manufacturing technologies to address nanometer design challenges such as low power, complex hierarchical designs, timing and SI signoff. The reference flow was developed using SMIC's 90nm process technology and validated with sample designs.

''Our collaboration with Cadence helps to drive our goal of continuing to enable the Chinese as well as global semiconductor market,'' said Paul Ouyang, vice president of design services at SMIC. ''The 90nm SMIC low power reference flow, fuelled by Encounter Timing System and other advanced digital IC design technologies from Cadence, along with SMIC's process technologies, will ensure high levels of quality and productivity for our customers, and offers a faster, validated, reduced-risk path to silicon."

The SMIC-Cadence Reference Flow is a complete RTL-to-GDSII, low-power flow focused on efficient energy utilization for 90nm SoCs. It consists of power awareness throughout all necessary design steps, including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation and complete signoff analysis. Encounter low-power flow is one of the industry's first complete low-power solution for the modern energy efficient SoCs.

In addition, this flow provides a comprehensive platform for designers to drive RTL-to-GDSII with emphasis on fast, accurate and automatic timing, power and SI closure. It addresses hierarchical block partitioning, physical timing optimization, 3-D RC extraction, IR drop, leakage and dynamic power optimization, crosstalk glitch and delay analysis. This flow enables designers to architect and optimize advanced designs in a systematic, predictable way, providing the highest quality of silicon.

''Our engagement with SMIC puts in place another vital link in our customers' design chain, ensuring a manufacturing aware design chain from idea to silicon. It also highlights the growing number of foundries and design houses in China that rely on the Cadence digital IC design flow," commented Mike McAweeney, VP of business development of industry alliances at Cadence.




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