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NEC introduces 'first' 55nm CMOS-compatible eDRAM tech

Posted: 14 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:NEC Electronics? 55nm? eDRAM? DRAM?

NEC Electronics Corp. and its subsidiaries, NEC Electronics America Inc. and NEC Electronics (Europe) GmbH, announced the industry's first 55nm CMOS-compatible embedded DRAM (eDRAM) technology.

An enhancement to NEC's patented metal-insulator-metal (MIM2) technology, the new eDRAM process is the industry's first combination of hafnium silicate film and nickel silicide, which has resulted in reduced power consumption and leakage current at this advanced node. Optimized for high-speed, low-power operation, the new process can be applied to SOC devices designed for a broad range of productsfrom mobile equipment such as cellphones and mobile handheld devices to digital consumer devices such as gaming consoles.

According to the press release, the introduction of hafnium silicate film to the embedded DRAM process allowed the company to reduce leakage current while increasing on-current by as much as 20 percent. Reducing the leakage current is an important factor to maintaining reasonable data retention time in eDRAM macros. In addition, the use of nickel silicide, a material suitable for aggressively scaled structures, helps to maintain low parasitic resistance of the scaled-down eDRAM cell and peripheral circuits and also reduce standby and operating power.

These new materials and the proprietary MIM2 technology enables NEC to deliver robust eDRAM solutions with smaller cell sizes, higher memory integration, ample storage capacitance and lower cell heights, and all the while maintain the merits of existing eDRAM technology, such as CMOS compatibility, low power and high-speed random access.

NEC' eDRAM uniquely combines DRAM density with SRAM-like performance, low latency and robust performance. With lower power consumption and a lower soft error rate than embedded SRAM, the company's eDRAM has blocks that can be rotated in any orientation on a chip to simplify integration with other on-chip components while preserving the performance and power consumption benefits afforded by NEC Electronics' process. The upper metal layers of an ASIC also can be routed over the top of eDRAM blocks to simplify chip design, improve timing and conserve silicon.

"By delivering the only CMOS-compatible eDRAM at the 55nm node, NEC Electronics is enabling designers to overcome the limitations of embedded SRAM and discrete DRAM components to achieve high-performance SOCs for next-generation applications," said Takaaki Kuwata, general manager, advanced device development division, NEC Electronics. "A combination of innovative materials and our mature MIM2 process, the new eDRAM offers low leakage power in a high-speed, high-density solution."




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