Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Networks

DSL chips target Internet Protocol TV

Posted: 18 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Ikanos? Fx100100? Fx100100S-5? VDSL/ADSL chipsets? Internet Protocol TV?

Ikanos Communications Inc.'s fifth generation of VDSL/ADSL chipsets offers optimized packet control and networking services for the anticipated growth in Internet Protocol TV (IPTV) services. Many incumbent carriers view IPTV as a primary motivation for moves to VDSL2 networks in the last mile.

Ikanos is fielding versions of its new chipset for both central-office access multiplexers and client customer premises equipment, and is offering two speed grades for each chipset.

Piyush Sevalia, director of product marketing, said the Fx100100-5 family makes use of the Fusiv network processor that Ikanos acquired from Analog Devices Inc. earlier this year, although only in client designs offering integrated residential gateway services. Standalone DSL modems will tend to use only a transceiver, although Ikanos' transceiver design integrates an Xtensa core from Tensilica. Devices aimed at customer premises carry the "S" suffixe.g. Fx100100S-5.

The Fx100100 platform supports speeds of up to 100Mbps, including the 30MHz channel profile known as 30a, while the Fx10050 equivalent supports speeds of up to 50Mbps. Both speed versions support all common 8-, 12- and 17MHz profiles.

Each port on the host DSP Burst Mode Engine can support VDSL2, VDSL, ADSL2+, ADSL2 or ADSL. To support networks based on either Ethernet switches or external network processors, the family can interface to either RMII/SMII Ethernet interfaces or POS-PHY L2 or L3 network processor interfaces.

A typical system design using the family will include the eight-port Burst Mode Engine, implemented in 90nm CMOS; dual four-port analog front-ends, which perform rate conversion, implemented in 0.25?m mixed-signal CMOS; dual four-port integrated front-ends for filtering and amp functions, also in 0.25?m CMOS; and four dual-port line drivers with low-noise amps, implemented in 0.5?m bipolar for high-voltage drive.

Many QoS functions in the new chipset are aimed specifically at IPTV applications. Packet classifiers support four queues per port, while a dynamic rate repartitioning engine allows reallocation of bandwidth across channels. Fast control of Internet Group Membership Protocol supports fast IP channel changing for IPTV access. An on-chip interleaver/deinterleaver memory provides impulse noise protection, and supports erasure detection and decoding functions.

Sevalia said that Ikanos will provide reference designs for both complex residential gateways and simple bridge modems in the home. Multifunction STBs and gateways will use the Fusiv network processor.

- Loring Wirbel
EE Times

Article Comments - DSL chips target Internet Protocol T...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top