Spice tools rev speed, accuracy

Berkeley Design Automation (BDA) released in August two products that claim to speed Spice simulation by five- to tenfold while preserving full Spice accuracy. Analog FastSpice and RF FastSpice are aimed at advanced applications such as gigahertz ICs in nanometer silicon technology.

BDA emerged in 2005 with the PLL Noise Analyzer, a product based on "precision circuit analysis" technology that has its roots in a Ph.D. thesis by one of the company's founders. An enhanced version of this technology underlies the FastSpice products, and PLL Noise Analyzer—previously a standalone tool—will become an option on top of RF FastSpice.

"We were always building a general-purpose, advanced analog and RF verification capability," said COO Paul Estrada. "We decided to focus on a notoriously difficult market, which was PLL noise, as a way to narrowly enter the market and prove the technology." With more than 10 customers under its belt, including Panasonic, NEC, Faraday, Fujitsu and Thine Electronics, BDA decided it was time to broaden the technology's reach.

Fast Spice simulators are not new, but BDA's offerings are, Estrada said. "It's a new category of precision for fast Spice, which has full Spice accuracy with no compromise," he said. "Every fast Spice simulator shipped to date has made assumptions and approximations, and sacrificed some accuracy to get much higher performance."

Fast Spice simulators today, Estrada said, are primarily aimed at digital design. They require extensive "tuning" at the block level to handle multiple frequencies, he said. Analog designers may use them for functional verification, but can't use them to get accurate measurements, according to Estrada. Such simulators generally claim to be within 1 percent or 2 percent of Spice accuracy, but that's not good enough for analog measurements, he said. "Our customers care about microvolts, so we have to be perfect down to that level."

BDA's new products have "multirate" transient engines to handle multiple frequencies, require no tuning and can return accurate measurements, according to the company. "We're aiming at all advanced analog and RF designers," Estrada said. "We're looking for applications that are breaking the current tools, where people are using Spice tools and RF simulation tools, but only at great pain."

Analog FastSpice's transient engine provides time-domain analysis. It offers DC, AC and linear-noise analyses. RF FastSpice adds a stochastic nonlinear engine, harmonic-balance engine, unified time and frequency analysis, and period analysis. It provides periodic steady-state, AC, transfer function and noise analyses, as well as oscillator phase noise and jitter.

More capabilities
BDA is not presenting its new products as direct Spice replacements, however. The strategy, Estrada said, is to provide additional capabilities for tough blocks that might otherwise take many hours to simulate.

The FastSpice products are integrated with Cadence Design Systems' analog design environment and require no special models. They offer Synopsys HSpice and Cadence Spectre netlist compatibility. They take in Verilog-A, s-parameter and BSIM models—"everything people use today," Estrada said.

The simulators run a full Spice matrix solution and promise full Spice accuracy. If a customer finds an instance where that isn't the case, Estrada said, the company treats it like a bug and fixes it.

The speedup starts with the multirate transient engines, Estrada said. Existing Spice and fast Spice simulators, he said, use a single-rate engine, which is accurate but slow (Spice) or fast but inaccurate (fast Spice). To use existing fast Spice simulators, he said, designers have to "tune" blocks by breaking them up into small pieces that approach a constant frequency.

"We looked at the problem and said, these are multirate designs, so let's bring a multirate engine to the table," Estrada said. "It's a much tougher math problem, but if you get the right math underneath, you can get full accuracy and much higher performance."

A paper given by BDA at last July's RFIC Symposium pointed to advances in solving "stiff" differential equations—those with widely separated time constants. The paper says iterations can be reduced by minimizing the number of rejected time steps, and that the time steps and the order of integration can be changed during periods of relative inactivity in the circuit.

The FastSpice products are in use at Fujitsu and Thine, said the company. They're available starting at $95,000 for Analog FastSpice; RF FastSpice is a $40,000 option on top of that.

- Richard Goering
EE Times