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PowerQuicc performs multilayer processing

Posted: 18 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Freescale Semiconductor Inc.? PowerQuicc? processor? full deflation engines? pattern-matching engines?

A new dual-core member of Freescale Semiconductor Inc.'s PowerQuicc processor family features full deflation engines and pattern-matching engines that allow it to perform seven-layer processing tasks.

The MPC8572, introduced in July, could take on the duties of many traditional off-chip ternary CAMs and application-layer processors, including XML accelerators, though the company is careful not to claim it will eliminate such special-purpose chips.

Now in its third generation, the PowerQuicc processor family is based on PowerPC cores. Over time, it has added higher-layer functions that have moved into all seven layers of the Open Systems Interconnect protocol stack.

Rich Schnur, Internet Protocol services marketing leader at Freescale, said it has been evident for many years that ASIC development was taking hardware processing all the way up to application processing on the seventh layer, but that dedicated processing blocks had to await standardized approaches to deep-packet inspection. Earlier moves into IPsec encryption and Secure Sockets Layer virtual private network creation prepared Freescale to consider ways of accelerating processing for regular expressions such as XML statements.

While it is conceivable that a single-core MPC854x processor could serve seven-layer processing tasks, Freescale designers elected to use a dual-core architecture as the basis for the MPC8572. Both of the device's e500 cores feature a 32Kbyte data cache, 32Kbyte instruction cache and 1Mbyte L2 cache. Four dedicated accelerator cores are included for table lookup, crypto/security, deflation tasks and pattern matching.

The pattern matcher, which follows a design usually reserved for a dedicated FPGA, performs antivirus, intrusion-detection and intrusion-prevention tasks by scanning packets for signatures and header patterns. The deflation engine performs localized deflation of compressed packets to scan for viruses and spam.

The on-chip table lookup is based on a design from Freescale's C-Port network processors. It handles access control list tables for routing and longest-prefix match for IP forwarding. The chip has an embedded crosspoint switch fabric, with interfaces supporting both PCI Express and Serial RapidIO. Also on-chip are a DDR2/DDR3 SDRAM controller and multiple GbE media-access controllers.

Freescale also announced in July a security partnership with Kaspersky Labs for security signatures.

- Loring Wirbel
EE Times

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