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Leakage takes priority at 65nm

Posted: 18 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? EE Times? spotlight? silicon? eda?

As the first reports on 65nm design come in, the good news is that there seems to be no problems at 65nm that weren't present at 90nm. The bad news is that some of the problems that plagued 90nm get much worse at the new node.

Designers who have completed 65nm projects identify leakage current as the biggest problem, and they're turning to strategies that manage power, including multiple voltage thresholds and voltage "islands."

"Clearly, threshold and gate leakages are getting worse. New design techniques have to be adopted," said Dermot Barry, general manager for the system IC business unit at design services firm Silicon & Software Systems (S3).

Design-for-manufacturing (DFM) also becomes a bigger issue at 65nm because process variations worsen, sources said. And signal-integrity problems grow as wiring gets denser.

On the manufacturing side, resolution enhancement technology (RET) becomes more complex at 65nm, said Peter Rickert, technology development manager at Texas Instruments Inc. And process variations have much more impact. "A 1nm variation is a much higher percentage at 65nm, where we might be talking about a 40nm gate length vs. 50- or 60- at 90nm," Rickert noted.

Nonetheless, most designers say the move to 65nm is proving easier than the preceding shift, which took the industry from 130nm to 90nm. "I don't think there's a major disruption," said Sribalan Santhaman, VP of engineering at P.A. Semi Inc. Existing problems worsen, Santhaman acknowledged, but at least there are "no brand-new problems." And besides nickel silicide adoption for transistors, the 65nm shift involves no major materials changes.

Multiple voltage threshold
Barry noted that the conventional approach to multithreshold CMOS is to use two libraries. Designers implement as much logic as possible using a high-threshold voltage, which is slower, but has less leakage. They then select transistors from the low-threshold library for critical nets where timing is the priority.

Barry called the low-power processes offered at 90nm and 65nm "a misnomer," because they may lower leakage at the expense of higher dynamic power consumption. A high-performance process will lower dynamic power, but leakage may be higher. It's thus crucial to understand which power spec is more important for the given application.

Multiple supply domains complicate timing analysis, Barry noted, requiring more corner analysis than in the past.

Without statistical timing analysis, he said, "we just take a very conservative approach."

DFM techniques introduced at 90nm, such as via doubling, wire spreading and metal fill, are still needed at 65nm, Barry said. "The layout of your standard cells could be affected by the location of the poly, and bends in the poly can affect timing characteristics of the standard cell. EDA tool vendors are responding to these challenges, but at a slow rate."

Voltage islands
Leakage is a "big negative" at 65nm, so P.A. Semi created multiple voltage islands on the chip, Santhaman said. That raises challenges such as how to verify transitions in and out of sleep modes.

"If voltage islands operate at a low VDD, stay away from higher Vt cells because they won't scale well," Santhaman said. Voltage islands also complicate signal integrity, he said, because distributing power with low inductance becomes a problem.

Santhaman views statistical timing analysis as "almost mandatory" to produce reasonable yields at 65nm. He said that P.A. Semi is developing its own capability because EDA vendors aren't providing it yet.

"If you increase the channel length, you have a slower device, but with better leakage," said Heinz Schuetzeneder, Infineon's project leader for 65nm platform technology. "A thin gate oxide will be fast with high leakage, and a thick oxide will be slower with better leakage." Infineon also uses multiple voltage thresholds and uses multiple voltage domains, he noted.

Designers need to be aware of process variation windows, Schuetzeneder said, and for that, they need optimized libraries with yield parameters from foundry partners. "Statistical timing is part of our development concept because if you make all the corners and all the variations, you end up with an exponentially increasing development effort," he added. "We're looking to the EDA vendors. It does not make sense to have refinements five years from now--we need them now."

TI claims to have minimized leakage problems at 65nm with its SmartReflex technologies, a combination of adaptive devices, circuit design and software for solving power and performance management problems. TI taped out its first 65nm product in January 2005, Rickert said, and it's now getting close to volume production with that chip, a baseband product for cellphones.

Power distribution and IR drop are also more of a concern, because with chips running at 1.2V or 1V, "there is just not much headroom left," Rickert said.

However, Rickert said, 65nm doesn't require any changes in materials, lithography or tools, except for a new post-RET design-inspection tool that TI has purchased. And thus far, it looks like the yields will ramp up more quickly than they did for 90nm, he said.

FPGA designers see 65nm as the route to higher capacities, and they're pushing the limits of 65nm in terms of transistor count. But they also use a regular fabric with identical elements that are replicated many times, so the physical-design challenges are easier for them than for their counterparts in standard-cell design.

Other hurdles
Some headaches are still universal. "The first thing I'd say about 65nm is that power management is extremely difficult," said Brad Howe, VP of IC design at Altera Corp. "The second is that signal integrity is an increasing concern."

"Use an FPGA," is Howe's advice to those thinking about the move to 65nm. "We pre-solve these problems for the customer."

For those who still want to do ASIC or ASSP designs at 65nm, Howe had this advice: "Be prepared to invest in the infrastructure you need. You can't outsource this kind of thing. You can't buy a tool and make it go away. You really need to spend the money and have the infrastructure."

- Richard Goering
EE Times

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