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Re-thinking SoC design at 65nm, below

Posted: 18 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Deepak Shankar? Mirabilis? silicon? eda? spotlight?

Executives from major IC houses and EDA companies have been talking about the design challenges facing developers as soc designs move from 65- to 45- and 32nm.

At the Future Electronics Horizons Forum in Budapest, Hungary, AMD fellow Robert Ober and Mentor Graphics CEO Wally Rhines talked about the need to work at higher levels of abstraction to create design files that generate both the hardware and software needed.

Fortunately, they are not alone in the need for such tools. Many system-level design startups have also been moving in this direction. The good news is that as an industry, we are already more than halfway there--we are yielding significant improvements in the form of compact architectures, better algorithm implementation, multiprocessing speed, power trade-offs, memory access, and integration of hardware and software design flows.

System-level modeling
As SoC designs shift from 65- to 45- to 32nm, the system-level modeling space is much more complex due to the 30 percent to 50 percent increase in devices. This consists of both methodology- and application-specific modeling domains that overlap to some extent.

Methodology-specific domains consist of discrete-event, cycle-based, synchronous data flow and continuous time. These models of computation provide a modeling methodology for general classes of modeling problems. The discrete-event model of computation is used for digital portions of a design that may have a strong control flow component.

A discrete-event model of computation is efficient for higher levels of abstraction, as the current simulation time is based on deterministic synchronous and asynchronous events. Discrete-event models provide a user with both time-ordered (asynchronous) and concurrent (synchronous) event modeling capabilities.

A cycle-based model of computation is similar to a discrete-event model of computation with the proviso that the model is clock-driven, executing the simulation engine for each clock cycle. Cycle-based simulators provide a user with more modeling fidelity--they are often used for more detailed modeling of digital systems, including verification of the final design.

A synchronous data-flow model of computation is more DSP-algorithm-oriented. Internal processing of synchronous data flow- type models can be simpler than a discrete-event modeling engine, requiring the concurrence of tokens at each modeling block to start processing, and the generation of new tokens to subsequent modeling blocks.

New thinking
System-level modeling is evolving to solve the original problem of determining quickly and efficiently the impact of design specification change on the performance of a proposed system.

The design specification itself typically is a Word or Frame Maker document with text, block diagrams and tables. Simulation models contain more details, but are difficult to share with executive staff, marketing, manufacturing or field support because non-modelers lack the handling expertise commercial tools require. If the system- or golden-level model could be exchanged among design groups located around the globe as the design specification, a proposed change might be evaluated by the marketing organization directly.

Many advanced tools are beginning to address these issues. Mirabilis Design has developed a tool methodology based on the University of California's Ptolemy II to embed a system-level model into a design specification as a Java Applet. Any Internet browser can be used to view and simulate the embedded system-level model within an HTML document. Mathematica from Wolfram Research enables researchers to create interactive calculations on the Internet, and enables users to compute and visualize results directly from a Web browser.

As we move toward the goals outlined by Ober and Rhines, many technologies must evolve. As Rhines pointed out, merging the specification process and implementation is an enabling technology. Current behavior synthesis is focused on DSP-algorithm implementation using a narrow coding practice. For behavior synthesis to be truly valuable, the output must merge data- and control-paths. The implementation path for hardware and software is still disjointed. There must be better integration to ensure that system-level optimization is not lost during the synthesis process.

System specification occurs during the first 30 percent of the development cycle. Depending on the project schedule and the complexity of the new capabilities, this can vary from three months to several years. During this period, a number of architectures must be explored. System-specification exploration tools must be measured based on new metrics that determine the adequacy of these new tools: modeling time, ease-of-construction, breadth and depth of high-level modeling libraries, and open API to integrate legacy knowledge.

Previous generations of graphical modeling tools might advertise more than 3,000 libraries as a sign of modeling-tool maturity and robustness. If a new UWB model evolved, however, these 3,000 libraries' elements would have limited reuse for UWB, since many are previous-generation, application-specific libraries or bottom-up component libraries.

Quality over quantity
The design methodology used at Mirabilis focuses on the quality and integration of the system-level libraries, such that they are likely to be reused in a new technology or another system-level model. This approach allows integration of as many as 30 bottom-up component functions into a single, system-level, easy-to-use, reusable module. Four queue blocks replace 24 previous-generation queue blocks through polymorphic port support and block-level menu attributes, while improving simulation performance.

The industry is rapidly addressing the gaps in merging the concept-to-system specification design space. The challenges that still need to be tackled are making concept-to-system specification a standard curriculum at universities, increasing industry awareness, and early adoption.

A possibility is to form an IEEE forum for this emerging top-down design methodology, including the separation and mapping of behavior and architecture, and hierarchical design elements. Mirabilis adopted another approach: to tie up with universities and enhance the system-design experience in the classroom.

- Deepak Shankar
CEO, Mirabilis Design Inc.




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