FPGAs include SerDes, PCS block

The new ECP2M FPGA family from Lattice Semiconductor Corp. consists of low-cost devices that offer high-speed embedded SerDes I/O plus a pre-engineered physical coding sublayer (PCS) block.

Based on the LatticeECP2 low-cost architecture, this FPGA family also has been developed on 90nm CMOS technology using 300mm wafers. Previously, high-speed embedded SerDes serial I/O with speeds higher than 3Gbps has been available only on costly high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video and industrial equipment.

Priced at approximately one-third the cost of competitive SerDes-based FPGAs, the ECP2M FPGA family bridges the price/performance gap between low cost and high-end FPGAs.

The ECP2M devices also have increased on-chip memory capacity to support higher bandwidth, SerDes-based applications. ECP2M Embedded Block RAM capacity ranges from 1.2Mbit up to 5.3Mbits, representing up to a 400 percent increase over competitive low-cost architectures, according to the company.

Both the ECP2 and ECP2M FPGA families feature 375MHz block level performance, 18x18 multipliers, embedded memory, pre-engineered 400Mbps DDR2 memory interface support, full-rate (10Gbps) SPI4.2 support, configuration bitstream encryption and dual-boot configuration support. The ECP2M FPGAs also features an additional 4 to 16 channels of 3.125Gbps SerDes.

Samples of the first member of the ECP2M family, the ECP2M-35, in both 484 and 672 ball fpBGA packages will be available next month. Lattice plans to bring the entire ECP2M family to the market during the first half of 2007. The ECP2M-35 will be priced as low as $22.95 in 100,000-unit quantities for delivery in 2007.

- Ismini Scouras
eeProductCenter