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Lattice offers free reference design for FPGAs

Posted: 29 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Lattice Semiconductor? display interface reference designs? LatticeECP2? LatticeECP2M? FPGA?

Lattice Semiconductor Corp. announced the availability of a free display interface reference design that illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families to implement the 7:1 source synchronous LVDS interfaces commonly found in display applications.

Lattice also announced its plans for a series of daughter boards that can be used with the existing LatticeECP2 Advanced Evaluation board to quickly test this reference design for display applications. By integrating the 7:1 LVDS interfaces within its FPGAs, Lattice enables designers to reduce component count and system cost.

The display interface reference design takes advantage of the LatticeECP2/M devices' pre-engineered components that simplify the implementation of 7:1 LVDS interfaces. The LatticeECP2/M FPGAs contain integrated LVDS receivers and drivers capable of 840-Mbits/s performance. Built-in gearbox logic allows a 4X reduction in data rate before the data enters the Look-up Tables (LUTs) at the core of the FPGA. Built-in edge clocks minimize the skew between data and clocks. The pre-engineered components allow 7:1 LVDS interfaces to be easily constructed, without the need for manual placement of LUT logic within the devices.

The high-speed LVDS display interface reference design is available now for free download from the Lattice's website.

The display interface daughter cards designed for use with the LatticeECP2 evaluation board will be available for purchase in the fourth quarter of 2006.

- Ismini Scouras
eeProductCenter




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