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'Server-on-chip' opens road to universal I/O

Posted: 02 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:HyperTransport? Sun Microsystems? PCI Express? Niagara? AMD?

Sun Microsystems Inc. will pack native PCI Express and 10GbE interfaces onto its next-generation Niagara processor, the company announced in August. The resulting server-on-a-chipa first for the mainstream computer industrygenerated debate about the future of integrated I/O in the era of multicore microprocessors.

Some saw Niagara-2 as marking the first step toward someday putting programmable Serdes on a processor. That would effectively create a universal interconnect that could reshape how computers are built. Others argued that I/O integration will likely play a modest role in the future of computer CPUs.

Niagara-2 packs eight cores, each running up to eight threads in parallel, as well as hardware acceleration for cryptography, two 10GbE ports and eight lanes of PCI Expressfar beyond anything proposed by Intel Corp. or Advanced Micro Devices Inc.

"I see a lot of upside with PCI Express integration. It's a stepwise refinement on the road to universal I/O," said Michael Krause, an interconnect specialist in Hewlett-Packard Co.'s X86 server group, which competes with Sun.

In Krause's long-term vision, on-chip Serdes could be programmed on the fly to handle whatever interconnect protocol a system might requireEthernet, Express or even storage links like serial ATA. That could reduce the need for discrete "south-bridge" chips for I/O and potentially even eliminate expansion slots and cards.

The resulting systems would be highly simplified versions of today's servers, sporting a few CPUs linked by PCB traces to various connectors and devices. In this scenario, the cost-squeezed computer industry would undergo another massive consolidation in which many of today's third-party chip and board makers would wither away, their features sucked into an Intel or AMD processor.

Many observers see this vision as too extreme. I/O integration "sounds like a good idea at first blush, but when you start digging, it's not such a good idea," said Chuck Moore, a chief architect at AMD.

Systems gain little because they probably will still need discrete I/O chips, and CPUs will take on a huge burden because they will need to be validated against a fast-changing world of interconnect protocols and third-party devices, Moore said. Also, I/O features don't need the aggressive process technologies used for CPUs, he argued. Thus, Niagara-2 makes sense for Sun, but general-purpose server processors from AMD and Intel are not likely to follow suit, Moore said.

Ironically, AMD recently announced that its next-generation Opteron chips for servers will have four, rather than three, HyperTransport interconnects on board. AMD is also preparing to license its proprietary coherent version of HyperTransport. That move lays the groundwork for accelerator chips that directly attach to the Opteron. They could easily become cores sucked into future Opteron processors.

Security and networking are more important to integrate into server CPUs than I/O, said Renato Recio, an interconnect expert in IBM Corp.'s server group, which builds systems based on both the X86 and its own Power processors. Integrating I/O will be more strategic for desktops, where the cost of a discrete south-bridge chip is a larger percentage of the system cost than it is in expensive and complex servers, he added.

Even Sun takes a moderate stance on the future of integrated I/O. Putting programmable Serdes on-chip is "an interesting idea that's been kicked around, but it's risky," said Rick Hetherington, a chief architect for Niagara-2.

Sun put PCI Express and Ethernet on Niagara-2 to open up more I/O bandwidth and reduce the latency incurred when using discrete chips and boards.

The Ethernet blocks on Niagara-2 handle classification and filtering at L2, 3 and 4, so that incoming packets can be dumped directly into one of 16 receive DMA registers. The chip can support full 10Gbit line speed through the ports for packet sizes of 200Kbytes, Hetherington said. The Ethernet block takes up less than 7 percent of the die area of the 65nm processor.

Sun has working silicon on Niagara-2 that boots the Solaris OS and is being used to create prototypes to run industry benchmarks. Hetherington claims the chip is delivering nearly twice the performance of the first-generation part. Sun said it expects to respin the chip before it goes into production systems.

- Rick Merritt
EE Times




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