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Serial RapidIO-to-PCIe Bridge IP core reduces system development time

Posted: 10 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Mercury Computer Systems? PCI Express? Serial RapidIO? PCIe? IP cores?

Mercury Computer Systems Inc. announced what it touts as the industry's first Serial RapidIO-to-PCIe bridge IP core, which features complete protocol translation, an optimized dual-channel multi-threaded DMA engine and a pipelined PCI Express-to-RapidIO mapping table.

The Serial RapidIO-to-PCIe bridge IP core is designed for applications that require high-bandwidth bridging between PCI Express devices and Serial RapidIO fabrics and devices. It connects a 4x serial RapidIO port, operating up to 3.125GHz, to an 8X PCI Express port operating at 2.5GHz through an intelligent non-transparent bridge.

The Serial RapidIO-to-PCIe bridge IP core is intended to reduce development time for wireless infrastructure, storage and embedded system applications.

"Mercury's intelligent bridge IP core enables connectivity between processors that have only PCIe buses, to Serial RapidIO interfaces on DSPs from Freescale and TI, and Serial RapidIO switch fabrics from many vendors including Mercury," said Tracy Richardson, Director of the Silicon Solutions Group, for the Advanced Solutions business at Mercury, in a statement.

The Serial RapidIO-to-PCIe bridge IP core also provides a variety of system service features, including mailbox message queueing, PCIe MSI/MSI-X interrupt controller, RapidIO-to-PCIe Atomic transaction encapsulation, access protection, real-time event counters, and error management.

"Interworking has always been a priority in the development of the RapidIO standard, and increasingly we see a demand among engineers to enable bridging to a variety of standards-based interfaces," said Tom Cox, Executive Director of the RapidIO Trade Association. "With Mercury's new bridging IP, these designers can take advantage of Serial RapidIO system-level capabilities while leveraging existing devices such as multicore processors, network processors, and FPGA-based computational elements."

Mercury intends to leverage its relationships with several semiconductor suppliers to provide the bridge as either an FPGA netlist that will be supported by Altera, Lattice and Xilinx FPGAs; pre-programmed FPGAs; or license the IP for ASIC or FPGA environments.

The Mercury Serial RapidIO-to-PCIe Bridge IP Core is available now. Pricing information is available by contacting Mercury.

- Ismini Scouras

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