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VSIA forms verification IP quality workgroup

Posted: 10 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:VSI Alliance? verification IP? Freescale? Synopsys? LSI Logic?

The VSI Alliance (VSIA) announced that it has formed a verification intellectual property (IP) quality workgroup, which plans to create a verification IP quality worksheet to address the challenges facing designers as they evaluate and implement standard verification IP components. The workgroup is a subgroup of VSIA's IP quality workgroup, which is responsible for the creation of the VSIA quality IP (QIP) metric, VSIA said.

Companies involved in creating the verification IP quality workgroup include Cadence Design Systems Inc., Denali Software Inc., edacentrum, Freescale Semiconductor Inc., LSI Logic Corp., Mentor Graphics Corp., Synopsys Inc. and United Microelectronics Corp.

"As the adoption of the VSIA QIP Metric continues to increase, working to solve IP verification was a natural progression," said Kenneth Larsen, director of marketing strategy at Mentor Graphics and the VSIA verification IP workgroup chair. "Designers today face many challenges, and with a standardized mechanism to evaluate verification IP, we can minimize the risk and increase design productivity."

The VSIA QIP metric is a tool for helping to reduce the time required to make an IP purchase decision and integrate the core. The metric consists of spreadsheets that are filled out by IP providers to describe IP documentation, ease of integration, design quality and verification quality. Questions are ranked and scored, and the result is a metrics that should reflect the quality of the IP block, as well as the design and verification practices of the vendor.

The VSIA QIP metric was released to the public in January and has seen more than 1,000 unique downloads, according to VSIA.

- Dylan McGrath
EE Times

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