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ARM rolls out Cortex-R4F processor for automotive apps

Posted: 12 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ARM? Cortex-R4? processor? R4F? automotives?

ARM Ltd has started sampling the latest version of its Cortex-R4 processor that is targeted at reducing the cost and design-time of automotive applications.

ARM says the R4F processor offers floating point support for faster processing of 32bit designs, and enables designers to meet stringent error-free automotive safety standards while maintaining the flexibility of their SoC designs.

Error-Correcting Code
Features of the R4F include support for Error-Correcting Code (ECC) memory, the extension of error detection into the interconnect and a synthesis-optional Floating-Point Unit (FPU), and the company stresses the processor is fully supported by a broad range of ARM technologies including RealView development tools, ARM Artisan Physical IP and ARM PrimeCell peripheral IP.

The Cortex-R4F processor includes configurability during synthesis to optimize the processor for different applications through a high-resolution memory protection unit, caches, tightly-coupled memory, DMA and debug facilities. This configurability is provided without compromising the underlying ARM instruction set compatibility, maximizing the reuse of existing software investments by application developers and third parties.

It also brings a strong focus on safety with high resolution memory protection facilities to allow tight control over independent software tasks This is critical to applications based on the OSEK standard for an open-ended architecture, the JasPar Automotive software platform architecture, and the AutoSAR runtime environment.

ARM is a member of AutoSAR which has wide industry support with members such as BMW, Bosch, Continental, DaimlerChrysler, Ford, GM, Siemens and VW. ARM is also a member of JasPar, whose board members include Toyota, Nissan and Honda.

Error-free car safety
ARM says the Cortex-R4F allows its partners to meet error-free automotive safety standards through seamless support for error detection from the processor, through the interconnect and into peripherals, providing true system-wide protection.

The processor's embedded ECC memory also helps reduce the possible causes of system failure to increase network resiliency. The part features an advanced microarchitecture with dual instruction issue capability to deliver more than 800DMIPS in a performance optimized 90nm implementation, based upon an ARM Artisan Advantage library.

The company says the processor provides key savings in cost and power consumption for system developers, occupying less than 1mm? and consuming less than 0.27mW/MHz in an area-optimized 90nm implementation.

- John Walko
EE Times

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