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Memory IP core can be programmed at wafer or circuit level

Posted: 17 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Novocell Semiconductor? intellectual property core? IP memory core? IP core? NovoBlox?

Startup Novocell Semiconductor Inc. has rolled out an intellectual-property (IP) memory core that can be embedded into any standard logic CMOS device without special or post processing. The NovoBlox OTP Memory IP has the ability to be programmed at the wafer or circuit level or in the package, according to the company.

Novocell offers NovoBlox in two architectures: ROM and serial. The ROM architecture is a natural fit for a processor based system. The serial architecture features maintained outputs and a serial programming interface, making it suitable for fuse replacement.

''The NovoBlox SmartBit cell generates and confines the breakdown voltage entirely in the memory cell,'' said Charles Buenzli, Novocell's vice president and COO. ''This allows the unprogrammed cells to have the native reliability of the process while only the programmed cells see high voltage. Overall, this creates a highly reliable memory.''

NovoBlox has been silicon proven in a wide range of CMOS technologies ranging from 0.5 microns to 90-nm. It is scalable to 65-nm and beyond, according to the company. A typical NovoBlox license is $60,000 plus a per unit royalty.

- Mark LaPedus
EE Times

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