Aldec claims Verilog simulation speedup

Aldec Corp. announced that its new Riviera-Pro 2006.10 HDL simulator provides a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.

The speedup is a result of the company's new "system-level platform technology," according to Dave Rinehart, vice president at Aldec. He said the company has seen measurable gains at customer sites for ASICs and large FPGAs, and is planning additional optimizations that will add even more of a speed improvement, especially for SystemVerilog.

The new Riviera-Pro release also adds the ability to use generics in instantiations of SystemC modules in VHDL or Verilog code, and HDL block instantiations within SystemC code. Aldec claims that the visibility of SystemC objects in debugging windows is also improved. The simulator supports Microsoft Visual Studio 8.0 and newer versions of GNU C compilers.

The new release also extends support for SystemVerilog (IEEE 1800) and Property Specification Language (IEEE 1850). The enhancements affect both testbenches and design code.

New features requested by users have been implemented in the simulator's waveform viewer, including better zooming and scrolling, more alignment options, easier access to search options and support for new waveform formats. Aldec also claims that users of expression coverage can better control analyzed hierarchical regions of the design, and merge data from different sessions.

Other improvements include open intellectual property (IP) encryption for VHDL code, and faster compilation times and lower memory usage for both VHDL and Verilog. The Riviera 2006.10 release is available today and starts at $12,450, including the Riviera-SE and Riviera-Pro configurations.

- Richard Goering
EE Times