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IC design tool touts process-aware DFM

Posted: 18 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? Seismos? Paramos? process-aware tool? custom-IC design?

Synopsys Inc. will announce this week Seismos and Paramos, two "process-aware" tools that help custom- and analog-IC designers analyze the impact of transistor variability on circuit layouts.

The tools leverage technology-CAD (TCAD) data to bring accurate physical models into the design process, according to Synopsys.

Seismos is a transistor-level tool for the analysis of stress and other proximity effects in strained-silicon technologies. Paramos does a global extraction of process-aware Spice compact models, allowing users to run simulations that consider the impact of process variability. The tools are aimed at analog and custom digital designers, including those who create cell libraries and memories.

While the tools came out of Synopsys' TCAD development group, they are "true DFM products," said Terry Ma, Synopsys' group director of TCAD DFM modeling. "The overall idea is that we want to link manufacturing variation information back into design. TCAD tools run slowly, but we take manufacturing information and convert it into a set of models that run in a very efficient way."

The new tools work with Synopsys' IC Workbench layout editor. Ma said both offerings will run on the OpenAccess database within the next three to six months and thus will work with Cadence Design Systems' widely used Virtuoso editor. The tools do, however, require the use of Synopsys' Sentaurus process and device simulator to generate current-voltage (IV) and capacitance-voltage (CV) data.

At 45nm and below, Ma said, proximity and stress will have a greater impact on IC layouts. "Almost everybody at 45nm will have to go to strained silicon," he said. That shift, Ma said, causes systematic variations with stress proximity effects.

"When you go to strained engineering, you need to optimize stress in your transistors," he said, noting that if the same transistor is placed in two different areas, with different proximity effects, the behavior will differ. Users must understand those effects so they can create optimized layouts that have high yields, Ma said.

Seismos is run after routing, layout-vs.-schematic checking and extraction. The extraction can be provided by Synopsys' Star-RCXT tool, although Ma said customers have used third-party tools as well.

Seismos takes GDSII data, a device netlist, x-y coordinates of transistor gates, a technology file and a stress parameter file. The tool then calculates stress parameters and creates a model.

The output is an annotated Spice netlist that includes the device netlist plus instance parameters.

"We typically modify a couple of parameters in your Spice netlist, and those are the parameters that will affect overall transistor characteristics," Ma said

While Seismos is a transistor-level tool, Paramos is concerned with global die-to-die and wafer-to-wafer variations. It takes the IV and CV data from the TCAD environment, does a global Spice extraction and generates a "variation block" that can run in Synopsys' HSpice or in other Spice simulators.

Users can thus simulate the impact of process variability on circuit performance. Additionally, Synopsys claims that Paramos provides a physically based variation model for statistical timing simulations of circuit performance, allowing users to explore the design's sensitivity to real physical process parameters.

With information from the new DFM tools, Ma said, "I can go back and look at whether I need to optimize my process for the circuit, or change something in the circuit layout to reduce sensitivity."

Seismos and Paramos will work for fabless customers as well as integrated device manufacturers, Ma said. "What we have is a modification of the netlist. It doesn't disclose a lot of proprietary information about the process. We're working with foundries to make sure proprietary information is not disclosed."

The products are available now. List pricing is $150,000 for Seismos and $75,000 for Paramos.

- Richard Goering
EE Times




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