Xilinx ships new Virtex-5 LXT FPGAs

Xilinx Inc. has announced initial shipments of its Virtex-5 LXT FPGAs. The second of four domain-optimized platforms in the company's Virtex-5 family, the LXT platform series is said to be the first FPGA to deliver a hard-coded PCIe Endpoint and Tri-mode Ethernet MAC blocks. The Virtex-5 LXT platform also features the industry's lowest power 65nm transceiver, according to Xilinx, typically consuming less than 100mW per channel at 3.2Gbps.

Performance for triple play
The Virtex-5 LXT platform addresses the challenging bandwidth, power and cost targets facing equipment vendors working to enable the emerging "triple play" services market. The new platform is optimized to enable FPGA designers across a wide range of applications to benefit from serial connectivity by delivering a comprehensive, fully compliant protocol solution with the greatest ease of use.

"What started in the communication segment to improve bandwidth, cost and scalability is now becoming an industry-wide migration from parallel to serial interfaces across many applications within wired/wireless, video, storage, servers and consumer. A one-size-fits-all FPGA approach is no longer sufficient," said Steve Douglass, VP of product development at Xilinx. "The Virtex-5 LXT platform is the first of several high-speed serial platforms to be offered in the Virtex-5 family. The LXT platform is aimed at the large number of serial connectivity applications ranging from 100Mbps to 3.2Gbps."

In the multistandard serial interface market, PCIe and Gbit Ethernet have emerged as the leading interface standards in markets served by FPGAs and are expected to account for over 80 percent of all port shipments in 2009.

According to Xilinx, Virtex-5 LXT platform delivers the industry's first FPGA to offer a built-in PCIe Endpoint block and tri-mode Ethernet MAC, which gives designers an off-the-shelf solution that saves time, reduces power consumption and frees up valuable FPGA fabric resources. Built on the 65nm Virtex-5 platform with new ultrafast ExpressFabric technology, proven ASMBL architecture and low-power triple-oxide technology, the Virtex-5 LXT platform promises an average of 30 percent higher performance, 65 percent increased capacity and up to 35 percent reduction in dynamic power consumption over previous generation 90nm FPGAs. The hardened PCIe core saves users up to 10,000 LUTs and two watts of power as compared to soft IP core implementations.

Key features
Key features the Virtex-5 LXT family include:

• Low power transceiversUp to 24 RocketIO transceivers operating from 100Mbps to 3.2Gbps typically consuming less than 100mW per transceiver/receiver pair.

• Built-in PCIe blockFully compliant endpoint block that works with the RocketIO GTP transceivers to provide x1, x2, x4 and x8 PCIe interfaces.

• Built-in tri-mode Ethernet MAC blocksFour independent 10/100/1000Mbps blocks that work seamlessly with RocketIO transceivers.

• High signal integrityEight programmable levels of Transmit Pre-emphasis and four programmable levels of Receive Equalization address even the most stringent channels. Advanced diagnostic capability with the Chipscope Pro software toolset gives engineers the best signal integrity solution available.

• Widest protocol supportThe Virtex-5 RocketIO transceivers support a myriad of industry standards including PCIe, Gbit Ethernet, XAUI, SONET/SDH, CPRI and OBSAI, Serial RapidIO, HD-SDI and Fibre Channel.

• Off-the-shelf design solutionComplete protocol-based solution consisting of software, IP cores, reference designs, development kits, characterization reports, protocol compliance certification, collateral and design support.

Design software support for the Virtex-5 LXT platform is available this month. Virtex-5 LXT engineering samples are shipping today through the Xilinx Early Access Program in LX30T, LX50T and LX110T densities, with LX85T and LX330T to follow over the next six months.

At volume production timeframes in 2008, the LX30T device will list for $109, the LX50T for $189 and the LX110T at $529 in 1,000-unit volumes. These price points represent savings of more than 50 percent over competitive offerings for 90nm FPGAs, Xilinx said. For even further cost reductions, the Virtex-5 EasyPath program offers a 30 percent to 80 percent cost reduction and will be available at time of volume production. Xilinx will roll out complete, ready-to-go protocol solutions kits starting with the PCIe solutions kit in November 2006.