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IC firms collaborate with Synopsys to validate new ATPG tech

Posted: 19 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? automatic test pattern generation? ATPG? STARC?

Synopsys Inc. has collaborated with several semiconductor firms to test a new automatic test pattern generation (ATPG) technology designed to increase the quality of manufacturing tests by targeting small delay defects.

According to the company, the enhanced capability uses precise timing information from the Synopsys PrimeTime sign-off static timing analysis tool to test for small circuit delays that could result in timing failures when parts are run at-speed. Because traditional transition-delay ATPG does not directly target small delay defects, the new approach can further improve quality and reduce test escapes for digital ICs sensitive to small delay defects.

The Semiconductor Technology Academic Research Center (STARC), a research and development consortium founded by major Japanese semiconductor companies, has been working with Synopsys for the past two years to help develop and validate the technology. "STARC considers small delay defects a critical quality issue for our member companies as they design more circuits at 90nm technologies," said Takashi Aikyo, senior manager of the test and diagnosis group at STARC.

"Subtle process variations at 90nm and below can introduce small delays that adversely affect the most timing-sensitive paths in a design," said Graham Etchells, director of test marketing, Synopsys implementation group. "These small delay defects can remain untested using traditional transition- delay ATPG because it lacks the precise timing information required to explicitly target them. The new technology uses precise timing data from PrimeTime sign-off analysis to test small delay defects. We expect this innovation will result in a significant improvement in the quality of at-speed testing, leading to fewer test escapes and lower test cost."

Highly-accurate timing analysis is the key to testing small delay defects, Synopsys said. Designers can pass parasitic information from Synopsys' Star-RCXT sign-off extraction tool to the PrimeTime tool for static timing analysis, then use pin-slack information generated from the timing analysis to create small- delay-defect ATPG patterns. The new ATPG technology is consistent with existing design for test methodologies and does not require changes to a design, the company said.

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