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Samsung touts 'first' 50nm DRAM chip

Posted: 20 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:DDR2? DRAM? Samsung Electronics Co. Ltd?

Samsung Electronics Co. Ltd announced what it touts as the industry's 'first' 50nm DDR2 DRAM chip, which promises to step up production efficiency from the 60nm level by 55 percent.

The 1Gbit, 50nm DRAM with 3-D transistor design and multi-layered dielectric technology, uses a selective epitaxial growth transistor (SEG Tr). According to Samsung, this 3D transistor enables a broader electron channel to optimize the speed of each chip's electrons, reducing power consumption and allowing higher performance.

Adding to the 50nm design improvements, the SEG transistor introduces a multi-layered dielectric layer (ZrO2/Al2O3/ZrO2) to resolve weak electrical features. Moreover, the new dielectric layer sustains higher volumes of electron to increase storage capacity, ensuring higher reliability in storing data.

Furthermore, Samsung's proprietary recess channel array transistor (RCAT) technology has been adapted to work well with the 50nm DRAM process. RCAT effectively doubles the refresh term of DRAM and is a critical technology supporting higher scalability for the memory regardless of chip size. This key feature enables circuitry beyond 50nm.

"With the 50nm DRAM development, we're continuing our technology leadership, paving the way for our customers to reap not only greater cost efficiencies but also to make superior products," said Nam Yong Cho, executive VP of memory sales and marketing at Samsung's semiconductor business.

The 1Gbit 50nm chip encompasses three generations of DRAM technology70-, 60- and 50nmin achieving the most advanced level yet for DRAM mass production, said the company's announcement.

The 50nm process technology can be applied to a broad range of DRAM chips, including graphics and mobile DRAM. Mass production is slated 2008.

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