Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Synopsys unveils DFM tools for 45nm, beyond

Posted: 31 Oct 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? PA-DFM? Seismos? Paramos? design-for-manufacturing?

Synopsys Inc. has unveiled a new family of process-aware DFM (PA-DFM) products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs. As feature sizes continue to shrink, variability arising from advanced silicon technologies, such as strain engineering, increasingly affects circuit performance. The PA-DFM product family's core productsSynopsys Seismos and Paramoslink manufacturing variation information back to design, enabling custom IC (IP, cell, memory and analog) designers to optimize layouts and maximize yields. This product family is another key element in Synopsys' drive to help customers improve yields at every critical point throughout the design-to-manufacturing process.

The PA-DFM product family is uniquely equipped to account for transistor variability, a critical capability in the DFM space. These products address the parametric variations that arise from design and manufacturing interactions by integrating accurate physical modeling information in the design process. Building on Synopsys' TCAD expertise in advanced process and device modeling, these latest additions to the Synopsys DFM offering complement the company's recently announced PrimeYield suite of yield-analysis tools as well as its PrimeTime VX statistical timing analysis and Star-RCXT VX statistical extraction tools.

Seamless integration
To help ensure seamless integration with the existing design infrastructure, the PA-DFM products are built to easily "drop in" to customers' existing custom design flow and methodology, protecting their investment while fulfilling a critical need for reduced variability and increased circuit performance. The PA-DFM products allow custom IC designers to realize the full potential of technology scaling and, in turn, expand the latitude for yield maximization.

By integrating TCAD-derived models with physical design tools, Synopsys said it is uniquely positioned to fill a critical void in the design flow of nanometer ICs. Together with the company's industry-standard HSPICE circuit simulation tool and PrimeTime VX and Star-RCXT VX tools, the PA-DFM product family underscores Synopsys' focus on optimizing variation awareness for increased performance, productivity and predictability. All these tools are highly complementary, enabling customers to cover their bases with respect to variability issues from cell layout through design implementation.

Together, Seismos and Paramos address two major sources of variability in a design: proximity variations due to stress and other neighborhood effects, and global variations due to the spread of manufacturing process parameters across different die and wafers. By using accurate physical models of the manufacturing process, custom designers can account for manufacturing variability without major changes to the current physical design flow.

Stress, proximity effects
Seismos is a transistor-level tool for the analysis of stress and other proximity effects in nanometer strained-silicon technologies. As the 65nm technology node ramps to volume production and the 45nm technology node enters pre-production, customers need the capability to analyze parametric variations caused by proximity effects, such as the impact of layout on transistor stress state. Seismos is the first EDA tool to address this critical need. Its models are based on rigorous TCAD simulations validated by silicon data. The tool can easily handle multimillion-transistor designs.

Paramos links SPICE models directly to manufacturing conditions by extracting process-aware SPICE compact models that combine calibrated TCAD simulations with global SPICE extraction. It allows customers to simulate the impact of process variability (statistical or systematic) on circuit performance. This methodology provides customers with a physically based variation model for statistical timing simulations of circuit performance, allowing them to explore designs' sensitivity to real physical process parameters.

"At 45nm and below, our customers must understand both the impact of variation and the sources of this variation. Synopsys' new process-aware DFM product family provides our customers with increased understanding of the underlying physical phenomena that cause process variations," said Wolfgang Fichtner, general manager of the Synopsys TCAD business unit. "In addition, the tools allow our customers to take full advantage of Synopsys' TCAD, DFM and variation-aware statistical analysis technologies to explore and optimize their process and design methodologies, further closing the loop with silicon. This can lead to significant time and cost savings and, ultimately, to higher yield for chipmakers."

The PA-DFM product family is available now.

Article Comments - Synopsys unveils DFM tools for 45nm,...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top