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HDL Coder offers shortcut to IC design

Posted: 01 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:The Mathworks? HDL Coder? IC design? Matlab? Simulink?

Taking its boldest step thus far into IC design, The MathWorks Inc. introduced in September the Simulink HDL Coder, which automatically generates synthesizable Verilog and VHDL from Simulink models and Stateflow diagrams. The move gives thousands of Matlab and Simulink users a direct path to FPGA or ASIC implementation.

With its large user base, The MathWorks has already become a contender in the emerging ESL design market. According to the company, with the new link, users can design, simulate and validate system models and algorithms in Matlab and Simulink; automatically generate both hardware and software; and verify HW/SW implementations against the original system and algorithm models.

HDL Coder generates bit-true, cycle-accurate IEEE 1364-2001 Verilog and IEEE 1076 VHDL, along with testbenches and synthesis and simulation scripts. With the optional Link for ModelSim, users of that Mentor Graphics simulator can bring HDL code back into Simulink for cosimulation. With the optional Stateflow product, users can generate control logic from finite state machines (FSMs), in addition to generating data path logic from Simulink models.

Device independence
According to Ken Karnofsky, marketing director for signal processing and communications, customers are starting designs with MathWorks products and then doing HW/SW implementation. "There are significant demands from our customers to have a device-independent way to get from Simulink models into the HDL level of design. Capabilities to date tend to be specific to a device vendor's technology."

Karnofsky said, however, that Xilinx Inc.'s January purchase of Matlab-to-HDL provider Accelchip was not a driving factor in the release of HDL Coder. "We've been committed to this approach and strategy for several years," he explained, noting that The MathWorks already has a successful product that generates RTL code for digital filters from Simulink models. Customers wanted that capability to be extended in a more general way, he added.

According to Karnofsky, HDL Coder users will include systems and algorithm engineers who need a better way to hand off hardware specs. HDL Coder will also appeal to people who already have intellectual property (IP) in Simulink, as well as to DSP engineers looking for FPGA implementations.

Karnofsky acknowledged that there's been more interest and demonstrated acceptance among FPGA designers than ASIC developers for a Simulink-to-HDL link. But he noted that system architects in the ASIC community are using Simulink and that beta testers for HDL Coder represent a fairly equal mix of FPGA and ASIC designers.

Prior Simulink add-ons that generated HDLs required proprietary block sets or IP libraries, Karnofsky said. In contrast, with HDL Coder, users design with standard Simulink blocks. That makes it possible to have a single model that represents the golden reference design, avoiding separate models for hardware and software, he pointed out.

To generate HDL code, designers use a GUI or scripting mechanism to specify the implementation they want. A control file makes it possible to set parameters and specify serial, cascaded or parallel implementations. Users can choose the polarity, type and port name of the reset signal, along with language-specific options for Verilog or VHDL.

It's not behavioral synthesis, Karnofsky noted, because Simulink has a notion of time; HDL Coder doesn't start with an untimed description. Nonetheless, a transformation does take place.

Simulink is tied to HDLs. HDL Coder generates RTL Verilog and VHDL.

"Simulink has its own clock, but it's at the rate of the samples that are running through the Simulink engine, which is not the same as the clock rate of the chip," Karnofsky said. "The transformation goes from Simulink time to the actual clock time of the chip."

Initially, HDL Coder will generate Verilog or VHDL for blocks or subsystems, not entire chips. It will be for data path and algorithmically intensive designs, Karnofsky said, but not necessarily limited to those designs.

In addition to synthesizable VHDL and Verilog, HDL Coder provides a testbench that can be read by any simulation tool. HDL Coder also generates scripts for Synplicity's Synplify Pro synthesis tool and Mentor's ModelSim.

With The MathWorks' Link to ModelSim product, users can bring in legacy HDL code and cosimulate it in the Simulink environment. The newly generated HDL then includes the legacy HDL. This only works, however, for users of the ModelSim simulator.

Code comparison
One question that arises with any kind of automatically generated code is how it compares with handcrafted code in terms of quality. "The code is well-structured and commented," Karnofsky said. "We have customers who said they're very happy with the readability and the quality."

Karnofsky noted, however, that "we're not staking a claim in our first product to be equivalent to expert optimizations of HDL."

"I've done chip design for over 20 years," said Sudhir Sharma, HDL product manager at The MathWorks, "and in my experience, there's a wide range in the quality you get with hand coding. But here, because everything is captured at a high level in Simulink models, you're not so much worried about RTL. You're maintaining the Simulink model, and the beauty is that you don't have to read through code to understand the system."

HDL Coder sells for $15,000. Users must already have Matlab, Simulink, the Fixed Point Toolbox and Simulink Fixed Point. Recommended products include Stateflow, Link for ModelSim, Signal Processing Toolbox, Signal Processing Blockset and Filter Design Toolbox.

- Richard Goering
EE Times




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