Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Processors/DSPs

Quad-MAC DSP core suits compute-intensive tasks

Posted: 03 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:CEVA? CEVA-X1641? DSP core? CEVA-X? WiMAX?

CEVA Inc. has announced the CEVA-X1641the newest addition to the company's family of CEVA-X DSP cores and fully compliant with the CEVA-X Instruction Set Architecture (ISA).

The company said CEVA-X1641 is the first Quad-MAC DSP core in the scalable CEVA-X family and is designed specifically to run highly computational intensive tasks that require substantial data throughput and high memory bandwidth. The core is fully synthesizable with enhanced memory architecture. This provides customers with the flexibility to configure the optimal memory size and structure for their specific application such as WiMAX, WiBro, 3G Long Term Evolution (LTE), or advanced multimedia standards, including the evolving H.264 compression standard and VC1 main profile.

Like other CEVA-X ISA compliant cores, CEVA's latest DSP core is a combined VLIW/SIMD architecture, with additional features and enhancements required to handle the high-performance and data-throughput requirements of 4G technologies and multimedia applications. Highly computational intensive technologies such as WiMAX are calling for the use of four MAC units, coupled with a 128bit data memory bandwidth, to handle the extremely high data rates capable of reaching 100Mbps. Furthermore, CEVA-X1641 incorporates specialized video instructions and mechanisms to accelerate multimedia processing in applications like mobile TV and video conferencing, while reducing frequency and power consumption to extend the battery life of these fully featured mobile multimedia devices.

Cuts development time, cost
"The CEVA-X1641 DSP core is in line with our strategy to offer platforms that will support the growing need for performance and power-efficient DSPs for emerging wireless and multimedia standards," said Gideon Wertheizer, CEO of CEVA Inc. "Our new, high-performance and fully synthesizable CEVA-X1641 DSP core will enable customers to expedite their time-to-market and reduce development costs by using the same platform across multiple, differentiated products."

The VLIW architecture allows a high level of concurrent instructions processing, thus providing extended parallelism as well as low power consumption. SIMD architecture allows single instructions to operate on multiple data elements that result in code size reduction and increased performance. Low power consumption is achieved in CEVA-X1641 by its efficient instructions and dedicated mechanisms such as dynamic and selective unit shutdowns and clock gating.

The CEVA-X1641 provides a high-performance, low-power platform, the company said, allowing its licensees to develop multimode products and to reuse the same platform for next-generation standards such as 802.16e, WiBro, Flash-OFDM, UMTS and TD-SCDMA.

The CEVA-X1641, together with a complete software development tool chain, is available for immediate licensing.

Article Comments - Quad-MAC DSP core suits compute-inte...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top