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Test challenges could trump future chip designs

Posted: 03 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Robert Daasch? chip tests? Tets Maniwa?

Coming silicon process generations will bring not only immense increases in device density, but also the challenges of working with process and device variations that in many ways are worse than for the processes of 20 years ago, said Robert Daasch, professor of electrical and computer engineering at Portland State University.

In a talk at the International Test Conference, Daasch warned that "new combinations of materials, coupled with atomic-level granularity, will make the next generations of semiconductors much more susceptible to device variations."

The challenges, according to Daasch, will be the effect of device variations on designed chips and learning how the variations figure into chip test, and then managing the test process accordingly.

The changes in materials and the increasing device variability will lead to more statistical testing, Daasch predicted. Manufacturing processes will generate more defects in the base CMOS devices as features vary by single atoms. "The number and types of failure modes will increase to the point where we will see failures with no easily discernable physical cause," he said.

The novel devices may have inherent unreliability, unless the design takes process variability into account and integrates test into the design.

According to Daasch, diverging trends will shape the industry. Silicon defect levels will rise, and the resultant increase in fault models will put pressure on test costs. At the same time, statistical testing could reduce the number and duration of tests. As the defects increase, test will have to address the need for faster defect sorting. Test will also have to feed back information to enable remediation efforts on yield and reliability.

A statistical test framework can act at the data collection point and assist in creating adaptive test formats. In the long term, adaptive testing will lead to more dynamic testing that could result in different tests for each die.

Next-generation designs will have to address materials and test design simultaneously. Merely extending the current practices cannot anticipate the challenges that a unified materials-design-test process could conquer, said Daasch.

"Design schedules need to change and be shortened so test development and debug are not on the critical path," he said. "Otherwise, test will become the biggest bottleneck in product development."

- Tets Maniwa
EE Times

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