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Lattice unrolls PCIe cores for its 90nm FPGAs

Posted: 06 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Lattice? ispLeverCORE? LatticeECP2M? LatticeSCM? PCIe?

PCIe IP cores from Lattice

Lattice Semiconductor Corp. has expanded its ispLeverCORE portfolio PCIe IP cores, which are optimized for its 90nm LatticeECP2M and LatticeSCM FPGAs. The cores are designed to enable single-chip, programmable PCIe endpoints.

The core tailored for LatticeECP2M low-cost FPGAs implements a single-chip PCIe x1 endpoint with integrated Serdes that is suitable for high-volume, low-cost and limited form-factor applications. PCIe x1 and x4 cores for the LatticeSCM FPGA family are aimed at system applications requiring high integration.

The cores have been tested against PCIe Version 1.0a specifications.

The LatticeECP2M and LatticeSCM IP cores offer different approaches to implementing the PCIe protocol. Aimed at high-volume applications, the LatticeECP2M core implements the transaction, data link and most of the PHY in soft IP. The remainder of the PHY, including clock tolerance compensation, 8b/10b encoding and link synchronization, is embedded in the LatticeECP2M Physical Coding Sublayer (PCS), which fully supports 2.5Gbps operation.

The LatticeSCM family offers a high-performance FPGA fabric, feature-rich Serdes and PCS, as well as pre-engineered hard IP, or Masked Array for Cost Optimization (MACO), blocks implemented in ASIC gates that are suitable for high-throughput systems.

For PCIe, the LatticeSCM device uses its flexiMAC block to implement the PCIe PHY and data-link specifications. A separate MACO block also is dedicated to the complex Link Training and Status State Machine (LTSSM), leaving only the transaction layer implemented in FPGA gates. This pre-engineered product implemented in ASIC gates is said to minimize cost and power consumption for customers who want to use a high-performance FPGA for their PCIe design.

The LatticeECP2M and LatticeSCM PCIe products are available immediately. The IP cores are available within the IPexpress flow supported by Lattice's ispLEVER 6.0 Service Pack 1, or later, design tool suite.

The LatticeECP2M PCIe core can be downloaded from the Lattice Website and is available for a no-charge, time-limited evaluation within the IPexpress flow of the ispLEVER design tool. The LatticeECP2M device evaluation board is available with a x1 PCIe connector; for the LatticeSCM device, two evaluation boards are available with x1 and x8 PCIe connectors, respectively.

- Ismini Scouras
eeProductCenter




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