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Xilinx unveils new design solution for Virtex-5 LXT

Posted: 06 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Virtex-5 LXT? Xilinx? ISE design tools? ISE design tool? FPGAs?

Xilinx Inc. announced the availability of a complete logic design solution including an update to its Integrated Software Environment (ISE) design tools for their newest Virtex-5 LXT Platform FPGAs.

Announced recently, the Virtex-5 LXT FPGAs are touted to be the industry's first FPGA to deliver hard-coded PCI Express technology and Tri-mode Ethernet Media Controller (MAC) blocks. ISE 8.2i delivers a unique integrated timing closure environment and productivity-enhancing features, allowing users to fully exploit the connectivity, performance, and power advantages of the Virtex-5 LXT family. Updated tools include the latest service packs of the 8.2i versions of ISE Foundation, ChipScope Pro, and PlanAhead Design and Analysis Tool.

ISE 8.2i provides an implementation environment optimized to leverage the superior routing architecture of the Virtex-5 family and it's enhanced diagonal routing which supports block-to-block connectivity with minimal hops. The release provides access to the many features of the Virtex-5 LXT including the industry's lowest power 65nm transceiver, typically consuming less than 100mW per channel at 3.2Gbps.

Complete design solution
The rich feature set of the ISE 8.2i design suite enables designers targeting Virtex-5 LXT devices to meet performance goals with greater certainty and reach design closure in less time. Xilinx users can maintain industry leading performance in even the largest FPGA design. With its unique Fmax technology, ISE delivers features such as next-generation physical synthesis with critical pre and post routing optimization for Virtex-5 LXT designs. Enhanced physical synthesis support for the new ExpressFabric technology reduces levels of logic and signal delay while packing designs more efficiently.

ISE Foundation 8.2i: Xilinx flagship design environment delivers a complete, front-to-back design solution. ISE Foundation 8.2i includes an integrated timing closure environment offering tighter correlation between logical and physical design domains. Automated cross-probing between constraint entry, timing analysis, floorplanning and implementation reports provides greater visibility and more efficient method for timing closure and debugging designs.

ChipScope Pro 8.2i: Enables on-chip debug at or near operating system speed. Available as an add-on option, the ChipScope Pro 8.2i solution reduces verification cycles by up to 50 percent. ChipScope Pro 8.2i users can now take advantage of on-chip verification for designs which take advantage of the integrated PCIe block of the Virtex-5 LXT family of Platform FPGAs.

WASSO analysis
PlanAhead 8.2 allows designers to utilize a block-based design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options to avoid problems downstream. Used in conjunction with ISE 8.2i, PlanAhead 8.2 software delivers a two-speed grade performance and cost advantage over competing offerings. PlanAhead 8.2 also includes functionality to perform WASSO Analysis on Virtex-5 LXT FPGA designs, allowing users to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.

Support for the Virtex-5 LXT Family of Platform FPGAs is available for download from Xilinx's website. This offers additional device support for ISE Foundation customers on all supported platforms.

PlanAhead 8.2 is available on all major operating systems as an option to the Xilinx ISE design suite. Single-user licenses start at $5,995 list and include training. Multiple user licenses and training packages are also available. Free 30-day evaluation licenses are available for download.

- Clive Maxfield
Programmable Logic DesignLine




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