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Equivalence checker eyes clock gating

Posted: 08 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:sequential equivalence checkers? Calypto Design Systems? automation? clock-gating circuitry? clock-gating circuitry verification?

The sequential equivalence checker that Calypto Design Systems Inc. will release soon promises to automate the verification of clock-gating circuitry.

Slec CG (clock gating) expands Calypto's lineup. A pioneer of sequential equivalence checking, the company offers the Sequential Logic Equivalence Checker (Slec) System, which verifies C-language designs against RTL code, and Slec RTL, which verifies that sequential changes in RTL code don't impact functionality.

Mitch Dale, director of product marketing at Calypto, said Slec GC adds support for clock-gating structures such as anti-glitch latches and enable logic. It also supports sequential clock gating. It can be purchased as a standalone product that offers a subset of Slec RTL's capabilities, and the clock-gating capabilities will be added to Slec System and Slec RTL.

Devadas Varma, founder and chairman of Calypto, said many customers implement power optimization at the register-transfer level or higher. "We wanted to provide some solution to verify what people are doing day-to-day manually," he said. Slec CG users, he noted, can optimize a design for low power and make sure that the functionality of the design hasn't changed.

Clock gating can be combinational, Varma noted, if data doesn't change during the clock cycle; but if data does change, or the input to the clock is random, it's sequential. And that, said Varma, is where people typically get into trouble when it comes to verification.

Simulation is not a good solution, Dale said. Testbenches must be modified, because they're set up to look at active states, while clock gating leverages inactive states. Moreover, coverage can be insufficient, and long regression runs may be needed. And corner case bugs introduced by clock gating can be hard to find.

Slec CG promises 100 percent coverage. "For clock-gating changes, there is no need to run simulation," Dale said, though "of course the original RTL must be verified."

The input to Slec CG is the original netlist and the clock-gated one. A Tcl script provides information about latency and throughput. If the tool finds a functional difference, it generates a counterexample, providing a waveform the designer can use to debug the problem.

Built on patented "sequential analysis technology," Slec CG verifies all possible input sequences that enable and disable clocks. It identifies potentially invalid clock-gating logic, verifies the interaction of multiple clock-gated blocks and provides block-level debugging. The tool uses multiple formal solvers.

The product handles blocks of up to 500,000 gates. There are no further restrictions on RTL code. Slec CG is an RTL-only tool and does not verify that the clock-gating circuitry hasn't changed the timing.

It is available now at $125,000 for a year's license. Its capabilities will be included in the Slec System and Slec RTL offerings, and will be given to those tools' existing licensed users.

- Richard Goering
EE Times




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