Mirabilis toolkit generates Xilinx FPGA platform models

Mirabilis Design Inc. has joined the Xilinx ESL initiative to provide FPGA designers with architectural exploration solutions for feasibility studies and virtual prototyping of FPGAs and multi-FPGA systems.

The company also announced immediate availability of the new VisualSim Xilinx FPGA Modeling Toolkit that enables quick prototypes of new and derivative systems using parameterized models of FPGA platforms. With this virtual prototype, designers can select the right architecture by conducting rapid and extensive performance trade-offs during the product definition phase.

VisualSim is a graphical, platform-independent design environment that accelerates performance analysis and architecture exploration. Designers construct models using pre-built parameterized construction components and use the automated statistics and run-time visualization for ad-hoc analysis. VisualSim optimizes the initial concept through a series of modeling refinement and abstraction to deliver the best architecture as an executable specification. The toolkit accelerates performance analysis and architecture exploration of FPGA and multi-FPGA systems by introducing Xilinx IP component model generators with built-in statistics described as concurrent functional flows that are modeled as priority-based variable delays, instruction sequence or behavior descriptions. The virtual prototypes have built-in statistics generators that produce performance and power summaries including queue occupancy, percent utilization, effective throughput, power consumed per device, stall and idle times, cache hit-ratios, and end-to-end latencies.

VisualSim Xilinx FPGA Modeling Toolkit generates simulation models of the proposed system from user-entered information in a graphical template and spreadsheet without requiring any software programming. The Xilinx FPGA models are combined with standard and custom components from the VisualSim modeling library to create the virtual prototype of the full system. The models can be used by embedded system architects to optimize the resource allocation; partitioning into hardware and software; and experiment with functional flows.

The VisualSim Xilinx FPGA Modeling Toolkit contains parameterized generators of processors (PowerPC and MicroBlaze cores), memories (block RAM, SDRAM and Caches), buses (CoreConnect PLB, FSL Bus and CoreConnect OPB) and communication devices (Ethernet and PCI). The toolkit also contains models of the popular Xilinx Virtex family of FPGAs including the new Virtex-5 devices. The FPGA platform, traffic sequence and software tasks are described graphically, and simulation runs are conducted by modifying various hardware attributes such as queue depths, resource speeds, bus widths, number of processors and memory sizes. Applications and algorithmic behaviors are described as concurrent functional flows that are modeled as priority-based variable delays, instructions sequences, or behavior descriptions. The virtual prototypes have built-in statistics generators that produce performance and power summaries including queue occupancy, percent utilization, effective throughput, power consumed per device, stall and idle time, cache hit ratios, and end-to-end latencies.

The VisualSim Xilinx FPGA Modeling Toolkit is currently available on Windows, Linux and UNIX. The library requires VisualSim Architect to simulate. Annual pricing for the toolkit starts at $5,000.

- Gabe Moretti
EDA DesignLine