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Cadence teams with IBM to accelerate ASIC design

Posted: 15 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design? IBM? Encounter RTL Complier? ASIC?

Cadence Design Systems Inc. has inked an agreement with IBM to incorporate Encounter RTL Compiler global synthesis and Cadence Encounter Test technologies into IBM's 65nm ASIC design kit. This new kit provides IBM's ASIC customers with an optimized path for automated test solutions and test logic-design processing at 65nm.

The collaboration offers IBM's ASIC customers a proven way to address logic-design challenges before handoff to IBM, accelerating the completion of higher quality designs. ASIC customers will gain access to Cadence Test and Synthesis technologies when they receive the 65nm IBM ASIC design kit.

"For nearly two years, IBM has worked closely with Cadence to ensure that our ASIC clients continue to benefit from a differentiated test methodology that helps reduce their test development resources by implementing automated test pattern generation and diagnosis," said Rich Busch, director, ASIC products business unit, IBM technology collaboration solutions. "This has been accomplished by using Cadence synthesis and test technologies which are key components of our methodology to deliver industry leading shipped-product quality level."

"We are delighted about the outcome of this effort with IBM and the benefits our ASIC customers will gain," said Jim Miller, executive vice president, Cadence products and technologies organization. "The new design kit, leveraging Cadence technologies, will enable ASIC customers to complete 65nm ASIC designs more predictably and with fewer iterations."




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