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'DFM too complex,' experts say

Posted: 16 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:design-for-manufacturing? DFM? Cypress? Infineon? Mentor Graphics?

Today's design-for-manufacturing (DFM) technology is too complex, speakers told the Bacus Photomask Technology Symposium last September. Instead, they suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology.

"DFM is too expensive or too difficult to comprehend," said Artur Balasinski, principal engineer for process integration technology development at Cypress Semiconductor Corp. He called for standardized, parameterized layout elements to improve manufacturability through better IC layouts.

Kai Peter, optical proximity correction (OPC) specialist at Infineon Technologies AG, outlined a lithography-friendly design methodology that Infineon is applying to library cells for digital IC layouts. He said the flow is now established and can detect "hot spots" in layouts that have passed design rule checking (DRC).

"It's hard to say anything controversial about DFM because we can't agree on what DFM is," said Fedor Pikus, software development engineer at Mentor Graphics Corp.'s physical-verification business unit. Mentor is developing a "yield server," he said, to link disparate tools and enhancements in an integrated approach to DFM.

Balasinski said optimized IC layouts mitigate process variability and simplify mask making. In choosing between two approaches to improve layout qualityincreasingly restrictive design rules or a correct-by-construction approach using optimized, parameterized cellsthe second option is vastly preferable, he said. "There are only a few layout elements and they should be easy to standardize," Balasinski said.

Focusing on analog/RF design, Balasinski said design problems like exponential leakage, capacitive coupling for RF and device mismatch can be eased by reducing process variations. But who should take the initiative, he askedprocess developers, CAD tool makers or designers?

As of today, Balasinski said, "manufacturing-for-design" (MFD) is preferred over DFM by a wide margin. For example, he said, it's generally preferred to fix device mismatch through the MFD approach of exposure correction, rather than the DFM approach of design rules for pitch and orientation. That means DFM's cost must be reduced, he said.

Hope's there
In today's design flow, Balasinski said, design is too far from fabrication, CAD groups have no manufacturing-related responsibilities and manufacturing comes too late to change layouts. But there's hope for improvement. "We only have a few important layout elements to standardize, and we need to make sure the designer has the right portfolio to pick from," Balasinski said.

The parameterized cells would follow a correct-by-construction process, ensuring, for example, that the minimum critical dimension is sufficient to ensure device printability and quality. The design flow would simplify, Balasinski said, because designers would pick from a fixed set of layout elements. Showing a sample layout, Balasinski said better-quality cells do not necessarily result in larger areas.

Standardized, parameterized layouts have a number of advantages, Balasinski said. Beyond saving on design-rule development, he said, these advantages include better correlation of simulation to silicon, improved control of process variations, a controlled OPC environment, reduced variability, better control of the area-vs.-quality compromise, and improved control and metrology of the mask's critical dimension.

In response to a question, Balasinski said Cypress' own CAD department has emphasized design rules, "but is coming to understand that it's better to use parameterized layouts, because more design rules mean more trouble."

While Balasinski focused primarily on analog/RF circuits, Infineon's Peter discussed the library cells that underlie digital chip layouts. He described a "push-button" methodology that uses Mentor's Calibre Litho-Friendly Design (LFD) capability, which aims to provide designers with the necessary information to create a layout that is less sensitive to lithographic process windows.

Correct-by-construction IC design flow using standard layout elements could simplify design-for-manufacturing.

It's a challenge to introduce LFD into the design flow, Peter said, because the target user is a designer, not a lithography engineer. So, he said, "there must be simple parameters or LFD indicators that can be sorted according to the severity of the problem." In addition, Peter said, the methodology needs to indicate lithography hot spots and optimize layouts to remove them.

The development of library cells starts before the process freezes, Peter noted. One problem is thus the availability of early, robust process models. It's also important to have specifications for process windows, he noted, because a wide process variation can result in numerous problems that are hard to fix.

Infineon's flow starts with the drawn library cell, runs OPC with preliminary process models, and offers "scores and hints" for layout improvement. Designers can then modify the library cell's layout. The process has a "DRC-like look and feel," Peter said.

There's still work to be done, however. Peter noted that the flow currently offers a "simple-hint capability" that needs to be improved in the future. He said Infineon hopes to move away from design rules to a model-based, simulation-driven approach using process windows.

A disparate task
Mentor's Pikus noted that DFM encompasses a range of techniques, covering all stages of the design-to-silicon flow. It involves different users who often don't speak the same language, has multiple goals that may be loosely defined or incompatible, and involves a growing number of complex rules and checks, he said.

Restricted design rules can simplify DFM by addressing a few chosen yield-loss areas, Pikus said. But they also hide DFM complexity instead of managing it, and are "just too rigid" to replace DFM optimizations, he said. The real answer, Pikus said, is to give the IC designer a complete, integrated solution.

Pikus outlined Mentor's Yield Server, which holds the DFM database and manages DFM tools and enhancements. It will take in analysis data, process data and optimization requirements. It will then export DFM information while resolving conflicts between tools and optimizations.

The Yield Server, Pikus said, will interact with the designer and let the designer choose different abstraction levels. It can supply DFM analysis data to various tools. It can provide an overall design-level view, a cell-level view and a detailed polygon-level view of manufacturability issues.

The Yield Server will simultaneously consider multiple enhancements from different tools, he said, and undo any "problem enhancements." For example, Pikus said, doubling a via may increase vulnerability to bridging.

Audience members said the Yield Server sounds ambitious and questioned how it can become a reality. Pikus said Mentor will release the first portions of the framework this month. "As our knowledge increases, we will provide a higher level of technology," he said.

In the same Bacus session, Chul-Hong Park, a PhD candidate at the University of California at San Diego, discussed a fast "dual-graph" way to detect lithography hot spots. He called the approach a hybrid between rule-based and simulation-based methods of detecting the hot spots. Results are similar to simulation-based approaches, but runtimes are much faster, Park said, albeit with a "small overhead" in terms of false detections.

Another paper in the Bacus DFM session described Dosemapper, an approach at Cypress Semiconductor to improve critical-dimension uniformity by using scanner actuators to compensate for CD errors. It could have a significant impact on IC manufacturability at 65nm and below, said Nazneen Jeewakhan, process engineer at Cypress.

- Richard Goering
EE Times

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