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Startup promises 'one-stop shop' for memory IP

Posted: 16 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Novelics? memory? memory IP? ASIC? Dave Bursky?

Startup Novelics calls its menu of embedded memory options sufficient to meet the needs of almost all ASIC designers, eliminating the need to work with multiple suppliers of memory intellectual property. By achieving that without requiring special processes or extra masking steps, the company says it can minimize costs and let customers leverage mainstream foundry processes, allowing intellectual property (IP) portability from foundry to foundry with minimal requalification requirements.

Today's ASIC designs often incorporate a mix of memory types to satisfy performance requirements. If memory blocks are implemented using intellectual property, the designer might typically have to deal with two, three or more suppliers to license such needed memory types as general-purpose SRAM, cache RAM, DRAM and non-volatile memory. But dealing with multiple vendors may not be necessary if Novelics delivers on its goal of providing a full range of memory IP to satisfy all design requirements.

The company, founded in 2005, has developed its own dynamic, static and nonvolatile memory cell structures for standard bulk-CMOS processes. To support the memory, Novelics' configurable memory generator, MemQuest, allows arrays to be optimized for power, density and speed, said co-founder and CEO Cyrus Afghahi.

Array of types
With more than 30 years of accumulated memory design expertise among its staff, the company has developed coolSRAM-1T, a one-transistor-per-cell static RAM; coolSRAM-6T, a low-power, high-speed SRAM based on the standard, six-transistor memory cell that can be used for general-purpose memory as well as for high-speed caches; special multiport register files; and first-in/first-out and content-addressable memory blocks (cool-FIFO/RF and coolCAM). In the nonvolatile arena, Novelics has created high-density embedded flash memory structures called coolFlash, one-time-programmable blocks dubbed coolOTP, multi-time-programmable blocks (coolMTP) and read-only-memory cells (coolROM).

Rich Wawrzyniak, senior analyst at market research company Semico Inc., called Novelics' broad selection of memory options exceptional for an independent memory supplier. Most companies, he said, offer just one memory typeSRAM or embedded DRAM or non-volatile memory. Various foundries and ASIC suppliers either have developed homegrown memory capabilities or have licensed a range of memory types so they can offer the mix needed by ASIC designers, Wawrzyniak said. The array of memory types offered by Novelics could make it a one-stop shop for memory IP, simplifying licensing.

Low power
With its coolSRAM-6T, Novelics delivers a low-power SRAM that it claims has the lowest power consumption in the industry for a standard CMOS implementationjust 100mW for a 1Mbit block, Afghahi said. To achieve that low level, the memory cells include patented circuit technologies to minimize leakage current and active power in both the memory core and the peripheral circuits, Afghahi said.

When implemented in the mainstream, 130nm LP process from TSMC, the memory arrays can clock at speeds of up to 300MHz. For yield optimization, the arrays can incorporate row and column redundancy, error checking and correction, and built-in self test.

Novelics has also developed circuits that perform overstress testing to weed out potential early-failure devices. And a high-speed option lets designers implement low-latency blocks for such functions as digital-signal processing, graphics and processor caches.

To deliver high-performance cache arrays, Novelics has optimized every phase of the SRAM access path to achieve the best architectural design, Afghahi said. When higher-density memory arrays are needed, the coolSRAM-1T can deliver memory arrays of up to 32Mbits using standard CMOS process flows with a density of 1.2mm2/Mbit.

The cell architecture for Novelics' one-time-programmable memory results in a high-density cell that effectively uses only 1.5 transistors per bit, according to the company. Capacitive coupling protects cells that are not to be programmed during writes. The resulting circuit has an extremely low write power, making the cell suitable for such applications as RFID and battery-driven devices.

Bulk flash memories are implemented in a low-power memory cell that does not require extra mask layers or doping steps, making it compatible with standard 130nm CMOS process flows. The cell structure is scalable, and Novelics expects to port the cell to 90nm soon.

- Dave Bursky
EE Times

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