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Consider a structured-ASIC design methodology

Posted: 16 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:structured ASIC design method? structured ASIC? FPGA? Rob Schreck? Altera?

More and more engineers designing advanced systems are considering structured ASICs because of their low unit cost, low power, high performance and fast turnaround. In a structured ASIC, such functional resources as uncommitted logic gates, memory, PLLs and I/O buffers are embedded in a pre-engineered and preverified base layer of the chip. The device is then customized with the top few metal interconnect layers. This requires far less engineering time than creating an ASIC from the ground up.

The ability to configure the circuitry on the chip with only a few metal layers reduces not only time and development costs, but also the risk of design errors. That's because the structured-ASIC vendor needs to generate the only metallization layers, which are relatively simple, compared with the many mask layers needed to fabricate the silicon.

Developing with a structured ASIC is not without risk, however. Errors in the logic design can still exist. One way to avoid silicon respins is to use FPGA prototyping and then convert the design from an FPGA to an ASIC.

FPGA prototyping is more successful for structured ASICs compared with standard-cell ASICs when the structured ASIC mirrors the resources available on the FPGA.

Here are some suggestions for using a structured-ASIC design methodology:


  • Establish a design methodology that you can use for a range of applications. Make sure your design teams are trained on the tools as well as the FPGA and ASIC architectures needed to create the best design.

  • Use a software development environment that reduces the risk of design problems, such as functional logic errors. The use of logic verification and simulation, along with prototyping the design in an FPGA, is a proven method.

  • Prototype your design with an FPGA using the FPGA features that give you the best performance and functionality. Also, generate the prototype with the intellectual property you need for the application.

  • Test your design in-system as much as possible to verify that it works according to requirements. Make sure the system is tested with the FPGA prototype across the entire voltage and temperature range that the system will experience.

  • Design the system to use either an FPGA or a structured ASIC. This approach achieves two goals. First, you can go into production with the FPGA and then change to the ASIC once it is available. That lets the system get to market faster. Second, if there is an unexpected increase in the demand for ASICs and supplies are insufficient, some systems with an FPGA can be manufactured.


  • Use an FPGA to prototype only logic and low-level I/O. This will limit your design to low-end gate arrays that won't provide the performance edge needed. Too often, only the logic is prototyped in the FPGA, leading to a misconception of how well the design really works in the system. Many designs also require high-speed memory interfaces. It is best to prototype, to ensure that the interface performs as required, particularly across voltage and temperature variations.

  • Choose an ASIC methodology based only on unit cost. That choice may save some BOM costs, but it will make the system uncompetitive. Include factors such as realistic development time and costs along with total engineering effort. In the long run, an FPGA with a structured ASIC can provide lower development costs and faster development turnaround time.

  • Consider only standard-cell ASIC technology for application-specific standard-product designs. Sometimes, structured ASICs or even FPGAs are the best option for the annual volumes and the need for fast time-to-market.

  • Choose the structured ASIC before you look at the market needs for the design. When you try to shoehorn a design into a structured ASIC that is too small or feature-limited, the result is a system that is dead-on-arrival at the market.

  • Consider only single-chip solutions. Sometimes the best way to create a system can be to use two devices rather than one large ASIC. Partitioning the design can reduce overall development time and simplify the design process. You can also reduce the risk of having to respin a large ASIC design.

- Rob Schreck
Sr. Technical Manager, Structured ASIC Group
Altera Corp.

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