Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Sequence revs clock power with PowerTheater 65

Posted: 20 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Sequence Design? PowerTheater 65? clock power? clock gating? RTL?

Sequence Design has announced its flagship product for RTL power estimation and managementPowerTheater 65which includes enhanced clock power estimation and reduction as well as improvements to stimulus generation and performance.

Clocks often consume 30 percent to more than 50 percent of the total power consumed by the chip. To manage these effects, PowerTheater 65 provides significant insights into where and how clock power is being dissipated. Making the new solution more "silicon-aware," the company has improved the tool's clock gating, clock tracing and clock power reporting capabilities.

PowerTheater 65's hierarchical clock gating provides added control on where the integrated clock gating cells are to be inferred. This applies to both common clocks and enable signals that are shared across hierarchical boundaries. Additional report information gives users a clear picture of the number of registers gated.

This new product incorporates enhancements to clock tracing for gate-level designs as well. Fundamental clock tracing algorithms have been extended, tracing clock distribution networks with higher accuracy and automation, using combinational and sequential timing arcs in the timing libraries to guide clock tracing. Reports for clock domain tracing record the power of all elements traced in the clock domain.

Well-known technique
Clock gating is a well-known technique to reduce power in clock networks. However, the quality of the reduction obtained is controlled by the design of the clock-gating enable signals. If the clock is enabled when data is not changing, the user is wasting power due to these unused clock toggles. A new clock enable condition power linter helps determine the effectiveness of the clock enables in a design by analyzing the relationship between the clock enable signal, clock signal and data signal for inferred registers in the design.

On the software and stimulus side, PowerTheater 65 enhances designer productivity by improving processing times to handle simulation data in the FSDB format. The FSDB interface in PowerTheater 65 is almost 10 times faster and consumes half the memory of its predecessor. Gate-level simulations provide the most accurate power numbers, yet are time-consuming to run. In this release, PowerTheater 65 has been extended to support gate-level vector-less power estimation, complementing the tool's ability to perform RTL vector-less power estimation. This allows designers to get early power estimates at both RTL and gate level, with and without stimulus. A final enhancement is PowerTheater 65's ability to read encrypted Liberty (synlib) format libraries.

The PowerTheater 65 release is available today. List price begins at $1,75,000 for a three-year TBL.

Article Comments - Sequence revs clock power with Power...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top