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Complete design tools roll for Virtex-5 LXT FPGAs

Posted: 23 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Virtex-5 LXT? ISE Foundation? ChipScope Pro? PlanAhead?

Xilinx Inc. has released a complete logic design solution including an update to its Integrated Software Environment (ISE) design tools for its latest Virtex-5 LXT Platform FPGAs, said to be the first FPGA to deliver hard-coded PCIe End-Point and Tri-mode Ethernet MAC blocks.

ISE 8.2i delivers an integrated timing closure environment and productivity-enhancing features, allowing users to fully exploit the connectivity, performance and power advantages of the Virtex-5 LXT family. Updated tools include the latest service packs of the 8.2i versions of ISE Foundation, ChipScope Pro, and PlanAhead Design and Analysis Tool.

The upgraded ISE provides an implementation environment to leverage the routing architecture of the Virtex-5 family and enhanced diagonal routing that supports block-to-block connectivity with minimal hops. The release provides access to the features of Virtex-5 LXT, Xilinx said, including the industry's lowest power 65nm transceiver, typically using less than 100mW per channel at 3.2Gbps.

The feature set of the ISE 8.2i design suite enables designers using Virtex-5 LXT devices to meet performance goals with greater certainty and reach design closure in less time, the company said. Xilinx users can maintain quality performance in even the largest FPGA design. With its Fmax technology, ISE delivers features such as next-generation physical synthesis with pre and post routing optimization for Virtex-5 LXT designs. Enhanced physical synthesis support for the ExpressFabric technology reduces levels of logic and signal delay while packing designs more efficiently, explained the company.

Complete solution
ISE Foundation 8.2i: Xilinx flagship design environment delivers a complete, front-to-back design solution. ISE Foundation 8.2i includes an integrated timing closure environment offering tighter correlation between logical and physical design domains. Automated cross-probing between constraint entry, timing analysis, floorplanning and implementation reports provides greater visibility and more efficient method for timing closure and debugging designs.

ChipScope Pro 8.2i: Enables on-chip debug at or near OS speed. Available as an add-on option, the ChipScope Pro 8.2i solution reduces verification cycles by up to 50 percent. ChipScope Pro 8.2i users can take advantage of on-chip verification for designs, which take advantage of the integrated PCIe block of the Virtex-5 LXT family of Platform FPGAs.

PlanAhead 8.2 allows designers to use a block-based design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options to avoid problems downstream. Used in conjunction with ISE 8.2i, PlanAhead 8.2 software promises a two-speed grade performance and cost advantage over competing offerings. The solution also includes functionality to perform WASSO Analysis on Virtex-5 LXT FPGA designs, allowing users to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.

Pricing, availability
Support for the Virtex-5 LXT Platform FPGAs is available for download from the Xilinx Download site. This offers additional device support for ISE Foundation customers on all supported platforms. For more information about the ISE 8.2i software suite, visit Xilinx. PlanAhead 8.2 is available on all major OS as an option to the Xilinx ISE design suite. Single-user licenses start at $5,995 and include training. Multiple user licenses and training packages are also available. Free 30-day evaluation licenses are available for download.

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