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Clear Shape solution promises fast DFM hotspot detection

Posted: 28 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Clear Shape? InShape? design manufacturability checker? Litho Yield Sensitivity? DFM?

Clear Shape Technologies Inc. has announced InShape, said to be the first model-based full-chip Design Manufacturability Checker that predicts accurate silicon shapes, providing designers the ability to do fast, accurate DFM hotspot detection of catastrophic failures. InShape's critical variation information is also a required input for fast and accurate eDFM analysis and optimization.

InShape uses a patent-pending, model-based, non-linear optical transformation algorithm that allows designers to quickly and accurately detect potential manufacturing failures during physical design that would otherwise be found after tape-out in mask or silicon. The compact models encapsulate all necessary RET, OPC, mask, etch and lithography effects on both device and interconnect, and predict accurate contours for the entire chip from drawn layout in a matter of hours.

InShape provides designer hotspot identification based on fab designated criteria or Clear Shape's Litho Yield Sensitivity (LYS) metrics. The non-linear optical transformation algorithm also allows generation of automatic fixing guidelines that are input into the user's choice of third-party physical design tools. InShape is easily integrated into current library, IP, custom analog and cell-based digital physical design flows.

"The fundamental change over the last few years is that the lithography roadmap is now fixed: 193nm and various RET/OPC techniques perhaps including immersion," said Yao-Ting Wang, Clear Shape's CTO and chairman. "Yet the resolution problem continues to worsen and the actual shapes on silicon are progressively variant from ideal shapes in DRC-clean GDSII. This leads to catastrophic and parametric failures and lower than entitled performance. With Clear Shape's proprietary fast full-chip non-linear optical transformation algorithm, designers can now leverage accurate silicon shapes and optimize their designs before tapeout."

Systematic shape variations
At 65nm, lithography, etch and CMP are factors in causing systematic manufacturing variations to surpass random variations as the prime limiters to catastrophic and parametric yield loss.

The interaction of the shapes within the optical proximity halo and the spatially partially-coherent lithography projection systems creates highly non-linear systematic variations at different process conditions that cannot be captured by rules or pattern matching. The consequence is that these systematic shape variations, dependent on specific layout shape context, result in predictable catastrophic errors such as necking (opens) and bridging (shorts). Furthermore, the shape variations of interconnect and gate have a non-linear impact on electric parameters such as timing, leakage power and signal integrity.

Traditional options to deal with manufacturing variation are no longer adequate at sub-90nm.

Post-GDSII OPC uncovers printability problems that frequently require actual design changes when there is limited freedom after tape-out, making design closure unpredictable.

Running post-GDSII OPC tools during layout isn't feasible, because it takes days per layer to run a typical design through OPC and it is impractical to provide proprietary OPC-recipes to designers.

DRC alone is inadequate to prevent catastrophic yield loss due to systematic shape variations; additionally, DRC rules to address growing DFM issues become prohibitive in number and complexity.

Designers can restrict their design style to try to improve yield, but this leaves both area and performance on the table and underutilize expensive leading-edge processes.

Only model-based predictive approaches that are not based on moving post-GDSII OPC tools to designer's desk are potentially fast enough to let designers uncover hotspots during design implementation and make real-time design adjustments to eliminate them.

Early hotspot detection
InShape design manufacturability checker performs fast hierarchical full-chip silicon contour prediction across process window during design. InShape guides the designer to make changes only when there is a problem due to process-design interaction, rather than forcing a rigid design style through over-restrictive rules on polygon placement.

With a model similar to DRC, designers run InShape on their layout to perform a model-based verification that complements DRC. InShape uses this GDS layout information, in combination with the fab technology files, to automatically produce a report flagging: DFM hotspots such as opens and shorts; contact coverage; gate variability; and line-end pull-back in the designers' original layout.

InShape sorts the hotspots identified by type and criticality. It allows a fast analyze-fix-verify cycle by providing hotspot markers as well as ECO fixing guidelines that can be easily exported to third-party layout editors and/or place and route tools. InShape's fast contour prediction allows what-if analysis to be performed, and pre-checked blocks can be excluded by name or marker layer.

InShape's full-chip hotspot reports are generated in hours, with performance that is linearly scalable with the number of CPUs. InShape's capacity has been tested to a half billion transistors, and meets the accuracy criteria for certification by TSMC and other foundries and IDMs.

InShape also produces critical dimension (CD) reports that can be utilized by Clear Shape's OutPerform eDFM parametric analysis and optimization product.

InShape pricing starts at $300,000 per master license per year. InShape is available on Linux platforms. Distributed Processing is also available at incremental pricing.




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