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Under circuit void makes thinnest chips

Posted: 30 Nov 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Institute for Microelectronics Stuttgart? wafer? silicon chips? IC die? thinnest chips?

The Institute for Microelectronics Stuttgart (IMS) has developed a method to create chip die that are just 20?m thick, claiming them as the world's thinnest silicon chips. The work was done in cooperation with the University of Stuttgart and is the subject of late paper accepted for the forthcoming International Electron Devices Meeting (IEDM).

IMS has been able to reduce the previous state-of-the-art by an order of magnitude by using a manufacturing technique to form cavities under the chips-to-be at a distance of a few micrometers beneath the wafer surface prior to the integration of the electronic circuitry.

After the circuits have been formed in the top layer the chips are broken off the wafer surface rather than being diced from thinned wafers.

Silicon wafers, as processed, typically have a thickness of about 1mm in order to provide sufficient mechanical stability and stiffness for reliable processing in automated silicon process lines. Recently, there has been interest in thin chips for applications embedded in paper and on flexible foils and for stacking in three-dimensional circuits.

Such thin chips are conventionally made by grinding and polishing the back surface of the wafer after processing and prior to dicing out the chips. Such processing enables minimum chip thickness of typically 200?m.

Using the IMS technique the wafers still have enough mechanical stability for processing, but the under circuit voids form a "dotted line" that provides a preferred line of fracture to break the die away from the wafer.

In addition, the bulk of the silicon wafer acts like a carrier for the chips and can be recycled, leading to cost reduction, IMS claimed. The technology will be presented as a late news paper at IEDM on Dec. 12, 2006 in San Francisco.

- Peter Clarke
EE Times Europe




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