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EDA vendor rivalry bogs single power spec

Posted: 01 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:power standard Common Power Format? Silicon Integration Initiative? IEEE? Unified Power Format? Accellera?

IC designers want one standard way to represent power intent throughout the design and verification flow, according to presentations at a Low Power Workshop in California. Standards organizations say they're taking note, but EDA vendor rivalry continues to fuel two separate efforts to develop a low-power description standard.

The workshop, convened by the Accellera standards organization and Silicon Integration Initiative (Si2), provided a forum for IC and silicon intellectual-property (IP) designers to speak outand so they did, with presentations from AMD, ARM, Nokia, NXP, Qualcomm, Sun Microsystems, Texas Instruments and Virage Logic. Speakers agreed on the need for a power description standard that's extensible, works across the entire flow, represents complex behavior, fosters IP reuse and is as simple as possible.

But the one thing they want mosta single, industry-wide standardremains elusive. Synopsys Inc., Magma Design Automation Inc. and Mentor Graphics Corp. are supporting Accellera's Unified Power Format (UPF) effort, while Cadence Design Systems Inc. is determined to take its Common Power Format (CPF) directly to the IEEE. Cadence won't donate CPF to Accellera, and its EDA rivals have thus far declined to support an upcoming IEEE CPF working group.

For some users, the dispute could be a deal breaker. Herve Menager, senior principal architect at NXP Semiconductors, had a warning for EDA vendors: Come up with a single standard format or NXP will go back to using its own. "Competition on formats is not a value differentiator," Menager said.

Indeed, a multiplicity of standards "will cost us, and will cost our users more," said John Goodenough, director of design technology at ARM. He said there's a danger of vendors engaging in "syntax wars" without understanding the underlying semantics.

"The No. 1 priority is convergence on a standard," said Steve Schulz, president of Si2. "People want to avoid conflict and redundancy, and they want to avoid the cost and delay of extra interoperability problems."

The ideal way to converge on a single standard, said Accellera chairman Shrenik Mehta, is for Cadence to donate CPF to Accellera. Synopsys, Mentor and Magma have already donated their technology. "A standard must be open, take the best ideas from everywhere, reuse whatever is possible and be inclusive so multiple people can contribute technology," he said.

But with CPF, Cadence already has a "simple, clean" solution for low-power specifications, said Chi-Ping Hsu, chief strategist for products and technology at Cadence. CPF was designed from the ground up to benefit the whole industry, he said. According to Hsu, it represents more than 100 man-years of effort and has received input from 14 member companies in the Power Forward Initiative.

"The formats so far donated to UPF are those in existing products," Hsu said. "They're all fragmented, and that's exactly what customers are complaining about." The presentations at the Low Power Workshop "provide yet another validation of what we are doing" with the CPF, he added.

Why it matters
Workshop presenters left no doubt that the lack of power standards is one of the biggest challenges facing chip designers today. David Peterman, manager of wireless EDA at Texas Instruments Inc., noted that SoC development requires the description of power intent, including such features as voltage islands, retention, isolation, level shifting and power switches. But EDA vendors provide a "hodgepodge" of solutions, each with its own formats and methods for describing power, Peterman said.

What's needed, he said, is a "single, clear, extensible user-controlled standard" that captures power intent once, supports logical and physical implementation and verification, works across design flows, addresses IP integration and reuse, and can later be extended to system-level design.

Mika Naula, global IC tools manger for Nokia Corp., observed that there's no consistent way to define power management, or agreement over whether it should be handled in an HDL, library-component or side file. Power management may require thousands of statements at the SoC level, he said, and must be expressed across 10 to 30 tools.

Rob Mains, senior distinguished engineer at Sun Microsystems Inc., said that a good target for standardization would be a representation for library cells. Oscar Siguenza, engineering director at Virage Logic, spoke of the need for functional, timing and physical library standards.

Both Si2's Schulz and Steve Bailey, UPF technical subcommittee chair, said the Liberty library format has already been extended to capture power information. But Cadence's Hsu noted that Liberty, offered as an open-source standard, remains under the control of Synopsys.

One requirement that came up repeatedly in user presentations is the need for a standard that's extensible, and can thus be applied to future needs. "We want to make sure we don't just close down and solve today's problems," said Gill Watt, engineering manager at AMD.

"We built CPF knowing that there's another 10 to 15 years of development," said Cadence's Hsu. "It's built on Tcl, so it's very easy to add and change things."

Both Hsu and Bailey said their respective standards efforts are starting with an RTL-to-GDSII focus, but will be extendable to the system level. CPF, said Hsu, goes all the way down to manufacturing and even includes PCBs.

Cadence is still hoping the IEEE will approve a CPF working group by year's end. Schulz, meanwhile, said his group remains optimistic there's an opportunity for convergence.

- Richard Goering
EE Times




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