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True Circuits rolls out silicon proven 65nm analog IP

Posted: 08 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:phase-locked loop? phase-locked loops? 65nm? delay-locked loop? delay-locked loops?

True Circuits Inc. has announced "silicon proven" phase-locked loop (PLL) and delay-locked loop (DLL) hard macros using Taiwan Semiconductor Manufacturing Co. Ltd's (TSMC) 65nm process. The macros target high-speed timing applications that require low jitter and low power.

True Circuits claims to have already licensed this 65nm IP to customers who have incorporated it into products that will begin shipping in 2007. The company also is working with other silicon foundries and IDMs to port its PLLs and DLLs to other 65nm processes.

True Circuits offers PLL and DLL hard macros in Texas Instruments, TSMC, United Microelectronics Corp. and Chartered Semiconductor processes spanning five process generations, from 0.25?m to 65nm. The PLLs perform clock generation, de-skew, frequency synthesis, jitter filtering and spread-spectrum functions. The DLLs delay a set of signals by adjustable fractions of a reference clock cycle independent of voltage and temperature, and serve high-speed DDR interface applications.

The PLL and DLL macros serve a variety of interface standards and chip applications. They are pin-programmable and reusable, and claim easy integration. PLLs are available in a range of frequencies, multiplication factors, sizes, and functions. The company's LockNow! technology claims to improve PLL lock times.

The hard macros are available for a per-use license fee with reuse options and no royalty fees. Deliverables include GDSII and LVS Spice netlists, behavioral and synthesis models, Library Exchange Format files, and user documentation.

- Richard Goering
EE Times




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