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Synthesis tool meets complex CMP design rules

Posted: 13 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Blaze DFM? synthesis tool? synthesis tools? IC design tool? chip design tool?

Every nanometer chip requires dummy metal fill to reduce topology variations caused by chemical mechanical polishing. Startup Blaze DFM Inc. will announce a technology that it claims provides an intelligent solution to the problem of dummy fill.

The Blaze IF synthesis tool inserts dummy fill patterns into a design layout and is said to optimally meet complex CMP design rules without requiring complicated scripts. It uses Blaze DFM's timing and power-analysis engines to maintain power and performance requirements while fill shapes are being added.

The tool follows the May introduction of Blaze MO, an optimization tool that changes gate lengths to improve leakage power and timing, and then annotates design data for optical proximity correction tools. While Blaze IF uses some of the underlying technology of Blaze MO, it doesn't require that tool in order to run.

According to Andrew Kahng, co-founder and chairman of Blaze DFM, metal fill is "one of the few knobs left" that designers can turn in pursuit of design goals such as timing correctness, signal integrity, IR-drop control and inductance control.

"At 65nm and below, the problem of dummy fill becomes much, much harder, and the types of rules one sees for enforcing smoothness are fundamentally beyond what shape engines can handle," he said. "So we treat the problem as a chip-scale global optimization, and find a globally optimum result."

Today, Kahng said, metal fill is typically handled through scripts implemented in the IC physical-verification flow. These scripts, he said, "more often than not just find empty areas, and slam down as much fill as will fit." More recently, there have been at- tempts to perform metal fill with routing tools. The problem there, said Kahng, is that metal fill is a global optimization problem, and routers aren't designed to think globally.

Further, said Kahng, traditional approaches to metal fill don't consider electrical needs such as signal integrity, IR drop and dynamic-power constraints. Blaze IF will place dummy shapes farther away from highly active switching nets, he said, making it easier to insert decoupling capacitors if they're needed. It can place fill closer to nets that have hold-time criticality, helping ensure the net isn't too fast, or place fill farther from nets that have setup-time criticality, so the nets aren't slowed down.

To make these decisions, Blaze IF runs incremental timing, signal integrity and power analysis. Kahng said the tool divides the chip into "millions of little squares" and figures out exactly how to fill each one. And it develops a solution for all chip layers simultaneously, he said.

"We have constraints that exactly capture the requirements of the foundry design rules," Kahng said. "If a solution exists, our tool will find it."

Blaze IF runs after placement and routing. It takes in layout data, timing constraints, extracted parasitics, activity factors and toggle traces. It does a layer analysis, runs an optimization to determine the exact amount of fill to place in each grid square and then inserts the metal shapes. Output is an updated layout file as well as timing- and power-analysis information.

The tool can optimize all chip layers simultaneously in a matter of hours on a single CPU, said Kahng.

Metal fill is traditionally accomplished by foundries. Dave Reed, Blaze DFM's vice president of marketing and business development, said that Blaze has tried the new product "with pretty much all of the major foundry design rules."

But Kahng thinks there's a bigger potential market for Blaze IF. "Increasingly, design teams want to run fill themselves, so they can get a complete, ground-up extraction and signoff that comprehends the presence of dummy fill shapes," he said.

Blaze IF is available this month starting at $250,000 per year.

- Richard Goering
EE Times

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