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AMD, IBM report results of 45nm IC project

Posted: 14 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:IBM? AMD? 45nm? 65nm? processor generation?

IBM and AMD have announced the early results of the use of immersion lithography, ultralow-K interconnect dielectrics and multiple enhanced transistor strain techniques on 45nm microprocessor process generation, at the International Electron Device Meeting early this week.

The two companies also unveiled plans to make available the first 45nm products using immersion lithography and ultralow-K interconnect dielectrics in mid-2008.

"As the first microprocessor manufacturers to announce the use of immersion lithography and ultralow-K interconnect dielectrics for the 45nm technology generation, AMD and IBM continue to blaze a trail of innovation in microprocessor process technology," said Nick Kepler, VP of logic technology development at AMD. "Immersion lithography will allow us to deliver enhanced microprocessor design definition and manufacturing consistency. Ultralow-K interconnect dielectrics will further extend our industry-leading microprocessor performance-per-watt ratio for the benefit of all of our customers."

Current process technology uses conventional lithography and has limitations in defining microprocessor designs beyond 65nm. In contrast, immersion lithography uses a transparent liquid to fill the space between the projection lens of the step-and-repeat lithography system and the wafer that contains the microprocessors. This significant advance in lithography provides increased depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell improves by about 15 percent due to this enhanced process capability, without using more costly double-exposure techniques.

Moreover, the use of porous, ultralow-K dielectrics to reduce interconnect capacitance and wiring delay is critical to further improve microprocessor performance as well as lower power dissipation. This advancement is enabled through the development of an ultralow-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining mechanical strength. The addition of ultralow-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

"The introduction of immersion lithography and ultralow-K interconnect dielectrics at 45nm is an early example of the successful transfer of technology from our research work at the Albany Nanotech Center to IBM's 300mm manufacturing and development line in New York, as well as AMD's 300mm manufacturing line in Germany," said Gary Patton, VP of technology development at IBM's semiconductor R&D center.

The continued enhancement of AMD and IBM's transistor strain techniques has enabled the sustained scaling of transistor performance while overcoming geometry-related scaling issues with migration to 45nm. The two companies reported that despite the increased packing density of the 45nm generation transistors, they have demonstrated an 80 percent increase in p-channel transistor drive current and a 24 percent increase in n-channel transistor drive current compared to unstrained transistors.

IBM and AMD started collaborating on the development of next-generation semiconductor manufacturing technologies in 2003, and will continue joint development efforts until 2011 for 32nm and 22nm process technology generations.




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