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Far-flung engineers spin Stratix III

Posted: 18 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Altera? Xilinx? Gartner? FPGA? Stratix III?

Altera Corp. rolled out in November its newest FPGA architecture, Stratix III, emphasizing power optimization, performance enhancements and the work of 400 engineers in multiple locations over the past few years. What shouldn't be overlooked, though, is the role of an old Ping-Pong table in Toronto, Canada.

That table is as good a symbol as any of how the deft handling of an acquisition had supercharged Altera's design prowess as the company developed its first 65nm device family. The Ping-Pong-playing engineers at the Ontario-based company Right Track CAD were central to the development.

The third generation of the Stratix family grapples with the thorny downsides of 65nm processesspecifically, leakage problems. The issue is bedeviling designers who want to exploit the speed and density benefits of 65nm processes, but who are seeing power budgets spiral out of control as oxides thin.

The architectural enhancements, process technology and software upgrades herald a technological smack-down at the high end with archrival Xilinx Inc., which rolled out its 65nm Virtex-5 family earlier this year. And in general, the move to 65nm enables both FPGA vendors to better compete with ASIC suppliers, whose need to ship in high volumes is increasingly under pressure as system makers leverage technology to ship more systems faster, but at lower volumesa sweet spot for FPGAs.

"While Xilinx was clearly first to 65nm with Virtex-5, Altera's 65nm Stratix III appears to be a very competitive flagship product," said Bryan Lewis, senior VP and industry analyst with Gartner Dataquest. "This new power technology.. could really improve total power consumption of larger plug-in systems."

While Xilinx got the jump on high-end products at 65nm, Altera has generally paced itself just behind its rivalintentionally. "If the product is released before the process can yield, then it would have a negative impact," said David Greenfield, senior director of product marketing for high-end FPGAs at Altera. "By bringing down defect density aggressively in advance of customers going to volume, we can expect to see a positive impact on margin, and in turn we can be a reliable supplier."

This is crucial because as recently as the second fiscal quarter, newer products drove 17 percent of Altera's revenue.

Stratix III doubles density and claims a 25 percent performance boost over the previous-generation Stratix II devices while reducing dynamic power up to 55 percent. Static power can be cut as much as 64 percent, Altera said.

As Altera and Xilinx engage in a price war on older generations, power becomes a key differentiator in new generations. Xilinx's Virtex-5 claims a 35 percent reduction in dynamic power through the use of power-optimized hard intellectual property and its ExpressFabric technology at 65nm.

For Altera, the work on 65nm began three years ago, when it began collaborating with fab partner Taiwan Semiconductor Manufacturing Co. to minimize power problems using techniques such as strained silicon, triple oxides and low-k dielectrics. This time around, it has also introduced a new twist with Programmable Power. Stratix as a family has always had logic-array blocks filled with 16 logic elements each. But Stratix III for the first time lets designers toggle between high performance or low power in a given array block. The family offers up to 338,000 logic elements and 10,000 blocks.

"The blocks were always lit in Stratix and Stratix II. Now we have a dimmer switch," said Misha Burich, Altera's senior VP of software and systems engineering. "Now we say, 'Let's light just enough to get what the customer wants.'"

To this end, Altera engineers turned the crank on the company's Quartus II design software, optimizing version 6.1 for power. Quartus' PowerPlay tool analyzes a customer's design during compilation to identify performance-critical paths. It then sets the appropriate blocks to high-performance mode, while all other logic is set to low-power mode.

Quartus' TimeQuest timing analyzer supports the Synopsys Design Constraints timing format. This allows designers to reach timing closure quickly, Altera said. Quartus II also supports multiprocessor designs and 64bit Windows, and comes with a new floor planner and editor.

Overall core power settings range from 0.9V to 1.1V in the high-performance setting.

Stratix III cuts static power by as much as 64 percent.

Deft acquisition
In 2000, Altera managers acquired Right Track CAD Corp., then a two-year-old FPGA tools company founded by four engineers from the University of Toronto, including noted FPGA academic Jonathan Rose. They were focused on HW/SW co-design and were beginning to develop a new place-and-route engine. Most of the original Right Track team remains, although Rose has returned to academia.

Altera managers engaged in the usual team-building exercises, but it was the Ping-Pong table that set the early tone. "We had a Ping-Pong table before the acquisition, and it wasn't taken away the next day," said Vaughn Betz, the co-founder of Right Track and now Altera's director of software engineering. "We actually wrote in the acquisition agreement that they couldn't take away the Ping-Pong table."

The arrival of the Right Track crew coincided with some internal soul-searching in San Jose, California. When the bubble burst, Altera lost market share in its high-end business, in part because it had placed a big bet on its Apex family, which struggled with efficiency issues.

At the same time, while process was driving things at 180nm, it "was clear" that that was going to start to break down at 130nm and 90nm, as leakage current reared its ugly head, Greenfield said.

Customers expect twice the transistor density each node on a device that runs at least 25 percent faster, yet they often have an inflexible power budget. The communications infrastructure where Stratix is a natural play has very tight power requirements, even in stationary devices such as routers and base stations, Burich said.

At this time, Altera executives began a more sustained attempt to pull customers into the architectural discussion, creating a Customer Advisory Board. More than 40 companies sit on that board today. "We brought in key customers to talk about their roadmaps and our roadmaps, and we looked for alignment," Greenfield said. "A lot of the success of Stratix is because the products were specified properly."

Working with the place-and-route wizards in Toronto, the IC design and synthesis groups in San Jose began "creating a whole experimental infrastructure in which we model the future FPGA architecture and simulate it," Greenfield said, comparing the process to "the way airplanes are modeled. We literally ran hundreds of thousands of experiments and compiles on it while tuning various features."

Samples of the first member of the Stratix III family, the EP3SL150, will be available Q3 2007.

- Brian Fuller
EE Times

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