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Perform full-chip verification for AMS ICs

Posted: 18 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:analog mixed signal chip verification? AMS verification? mixed-signal simulation technology? final verification? Olaf Zinke?

It's not only the number of transistors per chip that increases with the evolution to smaller geometries, but also the number of different functions integrated per chip. For an A/D mixed-signal chip, it means that the amount of interaction between the analog and the digital portions of the chip increases as well.

A chip containing only simple unidirectional A/D functionality can probably be designed and verified with a divided A/D simulation flow. In cases with bidirectional interaction or feedback, however, this method is no longer sufficient. Functional design failures and mixed-signal connectivity problems can't be prevented in such designs without using mixed-signal simulation technology. Detecting such design flaws before tape-out helps developers succeed with first silicon. It saves respin cost and helps ensure faster time-to-market.

Simulation during the design phase can be efficiently done using a top-down design methodology. Leading design centers worldwide are adopting top-down methodologies or at least using portions of this design style combined with the reuse of intellectual property.

While the top-down methodology is well developed and supported, the case for full-chip verification is not the same. Final verification, the very last simulation step before tape-out, is still mostly done as a separate phase.

One common practice is to verify the digital design portion represented in Verilog or VHDL and use digital pseudo-models for the analog blocks. The downside of this flow is that there is a specific step required to create the digital pseudomodels.

Another practice is to use fast Spice transistor-level simulators. But it is unlikely that speed and capacity even for the best-in-class fast Spice simulators are efficient enough for full-chip transistor-level verification of very large mixed-signal chips.

Verification solutions independent of the mixed-signal full-chip top-down design phases are not very practical. Mixed-signal testbenches need to be split or completely rewritten, and test vectors need to be generated. This not only is a lot of workit also means that it is very likely for connection failures to escape detection, negating the main reason for doing full-chip verification.

The key to overcoming such limitations is simulation technology that allows for concurrently simulating both large transistor-level blocks and models in Verilog-AMS and VHDL-AMS, the same languages that are used during the top-down design phase. A new type of analog mixed-signal (AMS) simulation technology is neededone that combines a fast Spice analog engine with a high-performance digital engine capable of simulating transistors, the standard AMS languages and, of course, the standard digital languages.

An efficient use of multilevel AMS verification allows designers to create a verification plan that defines several design configurations and related simulation measurements. Each configuration uses a transistor-level representation for the critical path of the functionality to be tested, while other blocks of the design are switched to high-level behavioral models.

Because of the equivalent behavioral language support, the step of creating the behavioral models specifically for this verification process is eliminated. The behavioral models written during the top-down design phase can be directly reused without an additional characterization step.

The methodology allows detailed AMS verification of the whole chip, with minimum time spent for the verification setup. It smoothly connects the design and verification processes, and it reuses the behavioral models and testbenches during the verification phase.

- Olaf Zinke
Senior Product Engineering Manager, Custom IC Design
Cadence Design Systems Inc.

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