Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Test tool optimizes data for IC yield

Posted: 18 Dec 2006 ?? ?Print Version ?Bookmark and Share

Keywords:LogicVision Inc.? Mentor Graphics? Yield Insight? BIST? Scanburst?

A lot of test data can be used in optimizing IC yields, but the information must be captured and analyzed to be useful. LogicVision Inc.'s Yield Insight product, rolled out at the International Test Conference in Santa Clara, California, is being offered as a solution.

LogicVision, best known for its memory and logic BIST technologies, also rolled out Scanburst, a product that brings timing information to Mentor Graphics Corp.'s ATPG and test-compression tools, allowing them to find small delay defects typically missed by conventional transition-delay ATPG tools.

Yield Insight provides what LogicVision calls "yield learning," a process in which test-failure data can pinpoint potential yield problems. LogicVision describes yield learning as an iterative process to identify yield limiters and to gather actionable information to improve overall yield.

"At 90nm and below, we're seeing a lot more performance-related defects," said Steve Pateras, senior director of strategic technology at LogicVision. "Test allows you to efficiently screen for these defects, and hopefully characterize them for you."

Useful test data, Pateras said, includes transition defects for logic and bit-level, timing-related failures for memories. "It's not just pins out, it's pins in," Pateras said. "You're looking at performance-related issues inside a die." A memory test, he noted, may find that a particular cell is underperforming, leading to additional design margins for that cell.

Yield learning takes place over three phasessilicon bring-up, characterization and yield ramp, and volume production. At each phase, information can be fed back to design, fabrication and test. If first silicon does not meet functional requirements, for instance, the cause could be a design flaw, a process issue or a lithography problem. This information may lead to a design modification or a manufacturing change.

To use Yield Insight, engineers would typically first run LogicVision's ETDiagnostics tool, which extracts and logs substandard die performance information from ATE systems. That data is then fed into Yield Insight, which accumulates data over multiple dice and wafers, analyzes data and looks for trends. It then provides what LogicVision calls "actionable information" for the design, fabrication and test functions.

The first release of Yield Insight is aimed at memory and lets customers leverage their investment in LogicVision's memory BIST technology. They can analyze yield issues down to individual memories, rows, columns and bits, and correlate failures to different environmental conditions. Users can also analyze and optimize memory redundancy schemes.

Yield Insight will be available in Q1 of 2007.

Yield learning puts positive spin on failure data. Yield insight product offers analysis and feedback.

LogicVision's other new offering, Scanburst, basically takes the burst-mode timing capability that's available with the company's BIST products and makes it work with Mentor's Fastscan ATPG and TestKompress test compression tools. It lets users of these tools insert scan and clock-control structures for at-speed testing.

Scanburst thus provides the timing information that ATPG needs to find small delay defects, which Pateras called a major source of failure at 90nm and below. LogicVision's burst-mode approach applies a single-capture at-speed test, providing for the programmable ramping of the clock activity before each test capture.

The technology could work with other ATPG solutions, Pateras said, but for now Scanburst supports Mentor Graphics' products. Full customer availability is set for the first quarter.

- Richard Goering
EE Times

Article Comments - Test tool optimizes data for IC yiel...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top